From mboxrd@z Thu Jan 1 00:00:00 1970 From: Borislav Petkov Subject: Re: [PATCH v9 5/6] arm64: zynqmp: Add DDRC node Date: Wed, 17 Oct 2018 18:52:52 +0200 Message-ID: <20181017165252.GG22535@zn.tnic> References: <1539581388-23963-1-git-send-email-manish.narani@xilinx.com> <1539581388-23963-6-git-send-email-manish.narani@xilinx.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Return-path: Content-Disposition: inline In-Reply-To: <1539581388-23963-6-git-send-email-manish.narani@xilinx.com> Sender: linux-kernel-owner@vger.kernel.org To: Manish Narani Cc: robh+dt@kernel.org, mark.rutland@arm.com, michal.simek@xilinx.com, mchehab@kernel.org, amit.kucheria@linaro.org, sudeep.holla@arm.com, olof@lixom.net, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org List-Id: devicetree@vger.kernel.org On Mon, Oct 15, 2018 at 10:59:47AM +0530, Manish Narani wrote: > Add ddrc memory controller node in dts. The size mentioned in dts is > 0x30000, because we need to access DDR_QOS INTR registers located at > 0xFD090208 from this driver. > > Signed-off-by: Manish Narani > --- > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > index 29ce234..a81d3b16 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > @@ -355,6 +355,13 @@ > xlnx,bus-width = <64>; > }; > > + mc: memory-controller@fd070000 { > + compatible = "xlnx,zynqmp-ddrc-2.40a"; > + reg = <0x0 0xfd070000 0x0 0x30000>; > + interrupt-parent = <&gic>; > + interrupts = <0 112 4>; > + }; > + > gem0: ethernet@ff0b0000 { > compatible = "cdns,zynqmp-gem", "cdns,gem"; > status = "disabled"; > -- Still needs DT folks ACK. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.