From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paul Walmsley Subject: [PATCH v2 1/2] dt-bindings: serial: add documentation for the SiFive UART driver Date: Fri, 19 Oct 2018 11:48:27 -0700 Message-ID: <20181019184827.12351-2-paul.walmsley@sifive.com> References: <20181019184827.12351-1-paul.walmsley@sifive.com> Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <20181019184827.12351-1-paul.walmsley@sifive.com> Sender: linux-kernel-owner@vger.kernel.org To: linux-serial@vger.kernel.org Cc: Paul Walmsley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Greg Kroah-Hartman , Rob Herring , Mark Rutland , Palmer Dabbelt , Paul Walmsley List-Id: devicetree@vger.kernel.org Add DT binding documentation for the Linux driver for the SiFive asynchronous serial IP block. Nothing too exotic. Cc: linux-serial@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman Cc: Rob Herring Cc: Mark Rutland Cc: Palmer Dabbelt Reviewed-by: Palmer Dabbelt Signed-off-by: Paul Walmsley Signed-off-by: Paul Walmsley --- .../bindings/serial/sifive-serial.txt | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/sifive-serial.txt diff --git a/Documentation/devicetree/bindings/serial/sifive-serial.txt b/Documentation/devicetree/bindings/serial/sifive-serial.txt new file mode 100644 index 000000000000..8982338512f5 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/sifive-serial.txt @@ -0,0 +1,21 @@ +SiFive asynchronous serial interface (UART) + +Required properties: + +- compatible: should be "sifive,fu540-c000-uart0" or "sifive,uart0" +- reg: address and length of the register space +- interrupt-parent: should contain a phandle pointing to the SoC interrupt + controller device node that the UART interrupts are connected to +- interrupts: Should contain the UART interrupt identifier +- clocks: Should contain a clock identifier for the UART's parent clock + + +Example: + +uart0: serial@10010000 { + compatible = "sifive,uart0"; + interrupt-parent = <&plic0>; + interrupts = <80>; + reg = <0x0 0x10010000 0x0 0x1000>; + clocks = <&prci PRCI_CLK_TLCLK>; +}; -- 2.19.1