From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dmitry Osipenko Subject: [RFC PATCH v2 15/17] ARM: dts: tegra30: beaver: Setup voltage regulators for DVFS Date: Sun, 21 Oct 2018 23:54:59 +0300 Message-ID: <20181021205501.23943-16-digetx@gmail.com> References: <20181021205501.23943-1-digetx@gmail.com> Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <20181021205501.23943-1-digetx@gmail.com> Sender: linux-kernel-owner@vger.kernel.org To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Thierry Reding , Jonathan Hunter , Nishanth Menon , Stephen Boyd , Marcel Ziswiler Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: devicetree@vger.kernel.org Set min/max regulators voltage and add CPU node that hooks up CPU with voltage regulators. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra30-beaver.dts | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index b0d40ac8ac6e..39941489d005 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1806,8 +1806,11 @@ vddctrl_reg: vddctrl { regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&core_vdd_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-always-on; }; @@ -1868,13 +1871,16 @@ }; }; - tps62361@60 { + core_vdd_reg: tps62361@60 { compatible = "ti,tps62361"; reg = <0x60>; regulator-name = "tps62361-vout"; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1500000>; + regulator-coupled-with = <&vddctrl_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-boot-on; regulator-always-on; ti,vsel0-state-high; @@ -2114,4 +2120,11 @@ <&tegra_car TEGRA30_CLK_EXTERN1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + core-supply = <&core_vdd_reg>; + }; + }; }; -- 2.19.0