[PATCH V2 1/8] dt-bindings: fsl: add compatible for imx7ulp evk

[PATCH V2 1/8] dt-bindings: fsl: add compatible for imx7ulp evk

[A.s. Dong]

Cc: devicetree@vger.kernel.org
Cc: Shawn Guo <shawnguo@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
 Documentation/devicetree/bindings/arm/fsl.txt | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index 7b964d8..9c7c788 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -101,6 +101,10 @@ i.MX7 SabreSD Board
 Required root node properties:
     - compatible = "fsl,imx7d-sdb", "fsl,imx7d";
 
+i.MX7ULP Evaluation Kit
+Required root node properties:
+    - compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";
+
 Generic i.MX boards
 -------------------
 
@@ -123,6 +127,10 @@ i.MX6q generic board
 Required root node properties:
     - compatible = "fsl,imx6q";
 
+i.MX7ULP generic board
+Required root node properties:
+    - compatible = "fsl,imx7ulp";
+
 Freescale Vybrid Platform Device Tree Bindings
 ----------------------------------------------
 
-- 
2.7.4

[PATCH V2 2/8] dt-bindings: fsl: add imx7ulp pm related components bindings

[A.s. Dong]

Add imx7ulp pm related components bindings

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v1->v2:
 * new patch
---
 .../bindings/arm/freescale/fsl,imx7ulp-pm.txt      | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt

diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt
new file mode 100644
index 0000000..75195be
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt
@@ -0,0 +1,23 @@
+Freescale i.MX7ULP Power Management Components
+----------------------------------------------
+
+The Multi-System Mode Controller (MSMC) is responsible for sequencing
+the MCU into and out of all stop and run power modes. Specifically, it
+monitors events to trigger transitions between power modes while
+controlling the power, clocks, and memories of the MCU to achieve the
+power consumption and functionality of that mode.
+
+The WFI or WFE instruction is used to invoke a Sleep, Deep Sleep or
+Standby modes for either Cortex family. Run, Wait, and Stop are the
+common terms used for the primary operating modes of Kinetis
+microcontrollers.
+
+Required properties:
+- compatible:	Should be "fsl,imx7ulp-smc1".
+- reg:		Specifies base physical address and size of the register sets.
+
+Example:
+smc1: smc1@40410000 {
+	compatible = "fsl,imx7ulp-smc1";
+	reg = <0x40410000 0x1000>;
+};
-- 
2.7.4

Re: [PATCH V2 2/8] dt-bindings: fsl: add imx7ulp pm related components bindings

[Rob Herring]

On Tue, 23 Oct 2018 11:49:08 +0000, "A.s. Dong" wrote:
> Add imx7ulp pm related components bindings
> 
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
> ChangeLog:
> v1->v2:
>  * new patch
> ---
>  .../bindings/arm/freescale/fsl,imx7ulp-pm.txt      | 23 ++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt
> 

Reviewed-by: Rob Herring <robh@kernel.org>

[PATCH V2 3/8] dt-bindings: gpio: vf610: add optional clocks property

[A.s. Dong]

On some SoCs(e.g. MX7ULP), GPIO clock is gatable and maybe
disabled by default. Users have to make sure it's enabled before
being able to access controller registers, otherwise an external
abort error may occur. Let's add the optional clocks property to
handle this case.

For ULP GPIO clock, it includes two separate clocks: one is for
GPIO controller Input/Output function clock while another is
GPIO port control clock for interrupt function.

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: linux-gpio@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
v1->v2:
 * new patch
---
 Documentation/devicetree/bindings/gpio/gpio-vf610.txt | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpio/gpio-vf610.txt b/Documentation/devicetree/bindings/gpio/gpio-vf610.txt
index 0ccbae4..ae254aa 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-vf610.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-vf610.txt
@@ -24,6 +24,12 @@ Required properties for GPIO node:
       4 = active high level-sensitive.
       8 = active low level-sensitive.
 
+Optional properties:
+-clocks:	Must contain an entry for each entry in clock-names.
+		See common clock-bindings.txt for details.
+-clock-names:	A list of clock names. For imx7ulp, it must contain
+		"gpio", "port".
+
 Note: Each GPIO port should have an alias correctly numbered in "aliases"
 node.
 
-- 
2.7.4

Re: [PATCH V2 3/8] dt-bindings: gpio: vf610: add optional clocks property

[Rob Herring]

On Tue, 23 Oct 2018 11:49:13 +0000, "A.s. Dong" wrote:
> On some SoCs(e.g. MX7ULP), GPIO clock is gatable and maybe
> disabled by default. Users have to make sure it's enabled before
> being able to access controller registers, otherwise an external
> abort error may occur. Let's add the optional clocks property to
> handle this case.
> 
> For ULP GPIO clock, it includes two separate clocks: one is for
> GPIO controller Input/Output function clock while another is
> GPIO port control clock for interrupt function.
> 
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Stefan Agner <stefan@agner.ch>
> Cc: linux-gpio@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
> v1->v2:
>  * new patch
> ---
>  Documentation/devicetree/bindings/gpio/gpio-vf610.txt | 6 ++++++
>  1 file changed, 6 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

[PATCH V2 6/8] dts: imx: add common imx7ulp dtsi support

[A.s. Dong]

The i.MX 7ULP family of processors represents NXP’s latest achievement
in ultra-low-power processing for use cases demanding long battery life.
Targeted towards the growing market of portable devices, the i.MX 7ULP
family of processors features NXP's advanced implementation of the Arm®
Cortex®-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D Graphics
Processing Units (GPUs).

This patch aims to add the initial support including:
1) CLK
2) GPIO PTC, PTD, PTE, PTF
3) uSDHC 1/2
4) LPUART 4/5/6/7
5) LPI2C 6/7

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v1->v2:
 * update clk part due to binding change
 * separate soc.dtsi from board.dts
---
 arch/arm/boot/dts/imx7ulp.dtsi | 323 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 323 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi

diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
new file mode 100644
index 0000000..795edc2
--- /dev/null
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -0,0 +1,323 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *   Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/clock/imx7ulp-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "imx7ulp-pinfunc.h"
+
+/ {
+	interrupt-parent = <&intc>;
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		gpio0 = &gpio_ptc;
+		gpio1 = &gpio_ptd;
+		gpio2 = &gpio_pte;
+		gpio3 = &gpio_ptf;
+		i2c0 = &lpi2c6;
+		i2c1 = &lpi2c7;
+		mmc0 = &usdhc0;
+		mmc1 = &usdhc1;
+		serial0 = &lpuart4;
+		serial1 = &lpuart5;
+		serial2 = &lpuart6;
+		serial3 = &lpuart7;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0>;
+		};
+	};
+
+	intc: interrupt-controller@40021000 {
+		compatible = "arm,cortex-a7-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x40021000 0x1000>,
+		      <0x40022000 0x1000>;
+	};
+
+	rosc: clock-rosc {
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+		clock-output-names = "rosc";
+		#clock-cells = <0>;
+	};
+
+	sosc: clock-sosc {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		clock-output-names = "sosc";
+		#clock-cells = <0>;
+	};
+
+	sirc: clock-sirc {
+		compatible = "fixed-clock";
+		clock-frequency = <16000000>;
+		clock-output-names = "sirc";
+		#clock-cells = <0>;
+	};
+
+	firc: clock-firc {
+		compatible = "fixed-clock";
+		clock-frequency = <48000000>;
+		clock-output-names = "firc";
+		#clock-cells = <0>;
+	};
+
+	upll: clock-upll {
+		compatible = "fixed-clock";
+		clock-frequency = <480000000>;
+		clock-output-names = "upll";
+		#clock-cells = <0>;
+	};
+
+	mpll: clock-mpll {
+		compatible = "fixed-clock";
+		clock-frequency = <480000000>;
+		clock-output-names = "mpll";
+		#clock-cells = <0>;
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		arm,cpu-registers-not-fw-configured;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <1000000>;
+		status = "disabled";
+	};
+
+	ahbbridge0: bus@40000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x40000000 0x800000>;
+		ranges;
+
+		lpuart4: serial@402d0000 {
+			compatible = "fsl,imx7ulp-lpuart";
+			reg = <0x402d0000 0x1000>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
+			clock-names = "ipg";
+			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
+			assigned-clock-rates = <24000000>;
+			status = "disabled";
+		};
+
+		lpuart5: serial@402e0000 {
+			compatible = "fsl,imx7ulp-lpuart";
+			reg = <0x402e0000 0x1000>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
+			clock-names = "ipg";
+			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+			assigned-clock-rates = <48000000>;
+			status = "disabled";
+		};
+
+		tpm5: tpm@40260000 {
+			compatible = "fsl,imx7ulp-tpm";
+			reg = <0x40260000 0x1000>;
+			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+				 <&pcc2 IMX7ULP_CLK_LPTPM5>;
+			clock-names = "ipg", "per";
+		};
+
+		usdhc0: usdhc@40370000 {
+			compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
+			reg = <0x40370000 0x10000>;
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+				 <&pcc2 IMX7ULP_CLK_USDHC0>;
+			clock-names ="ipg", "ahb", "per";
+			assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
+			bus-width = <4>;
+			fsl,tuning-start-tap = <20>;
+			fsl,tuning-step= <2>;
+			status = "disabled";
+		};
+
+		usdhc1: usdhc@40380000 {
+			compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
+			reg = <0x40380000 0x10000>;
+			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+				 <&pcc2 IMX7ULP_CLK_USDHC1>;
+			clock-names ="ipg", "ahb", "per";
+			assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
+			bus-width = <4>;
+			fsl,tuning-start-tap = <20>;
+			fsl,tuning-step= <2>;
+			status = "disabled";
+		};
+
+		scg1: scg1@403e0000 {
+			compatible = "fsl,imx7ulp-scg1";
+			reg = <0x403e0000 0x10000>;
+			clocks = <&rosc>, <&sosc>, <&sirc>,
+				 <&firc>, <&upll>, <&mpll>;
+			clock-names = "rosc", "sosc", "sirc",
+				      "firc", "upll", "mpll";
+			#clock-cells = <1>;
+		};
+
+		pcc2: pcc2@403f0000 {
+			compatible = "fsl,imx7ulp-pcc2";
+			reg = <0x403f0000 0x10000>;
+			#clock-cells = <1>;
+			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
+		};
+
+		smc1: smc1@40410000 {
+			compatible = "fsl,imx7ulp-smc1";
+			reg = <0x40410000 0x1000>;
+		};
+
+		pcc3: pcc3@40b30000 {
+			compatible = "fsl,imx7ulp-pcc3";
+			reg = <0x40b30000 0x10000>;
+			#clock-cells = <1>;
+		};
+	};
+
+	ahbbridge1: bus@40800000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x40800000 0x800000>;
+		ranges;
+
+		lpi2c6: lpi2c@40a40000 {
+			compatible = "fsl,imx7ulp-lpi2c";
+			reg = <0x40a40000 0x10000>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
+			clock-names = "ipg";
+			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+			assigned-clock-rates = <48000000>;
+			status = "disabled";
+		};
+
+		lpi2c7: lpi2c@40a50000 {
+			compatible = "fsl,imx7ulp-lpi2c";
+			reg = <0x40a50000 0x10000>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
+			clock-names = "ipg";
+			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+			assigned-clock-rates = <48000000>;
+			status = "disabled";
+		};
+
+		lpuart6: serial@40a60000 {
+			compatible = "fsl,imx7ulp-lpuart";
+			reg = <0x40a60000 0x1000>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
+			clock-names = "ipg";
+			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+			assigned-clock-rates = <48000000>;
+			status = "disabled";
+		};
+
+		lpuart7: serial@40a70000 {
+			compatible = "fsl,imx7ulp-lpuart";
+			reg = <0x40a70000 0x1000>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pcc3  IMX7ULP_CLK_LPUART7>;
+			clock-names = "ipg";
+			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+			assigned-clock-rates = <48000000>;
+			status = "disabled";
+		};
+
+		iomuxc1: iomuxc@40ac0000 {
+			compatible = "fsl,imx7ulp-iomuxc1";
+			reg = <0x40ac0000 0x1000>;
+		};
+
+		gpio_ptc: gpio@40ae0000 {
+			compatible = "fsl,vf610-gpio";
+			reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
+				 <&pcc3 IMX7ULP_CLK_PCTLC>;
+			clock-names = "gpio", "port";
+			gpio-ranges = <&iomuxc1 0 0 32>;
+		};
+
+		gpio_ptd: gpio@40af0000 {
+			compatible = "fsl,vf610-gpio";
+			reg = <0x40af0000 0x1000 0x400f0040 0x40>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
+				 <&pcc3 IMX7ULP_CLK_PCTLD>;
+			clock-names = "gpio", "port";
+			gpio-ranges = <&iomuxc1 0 32 32>;
+		};
+
+		gpio_pte: gpio@40b00000 {
+			compatible = "fsl,vf610-gpio";
+			reg = <0x40b00000 0x1000 0x400f0080 0x40>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
+				 <&pcc3 IMX7ULP_CLK_PCTLE>;
+			clock-names = "gpio", "port";
+			gpio-ranges = <&iomuxc1 0 64 32>;
+		};
+
+		gpio_ptf: gpio@40b10000 {
+			compatible = "fsl,vf610-gpio";
+			reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
+				 <&pcc3 IMX7ULP_CLK_PCTLF>;
+			clock-names = "gpio", "port";
+			gpio-ranges = <&iomuxc1 0 96 32>;
+		};
+	};
+};
-- 
2.7.4

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Re: [PATCH V2 6/8] dts: imx: add common imx7ulp dtsi support

[Rob Herring]

On Tue, Oct 23, 2018 at 11:49:25AM +0000, A.s. Dong wrote:
> The i.MX 7ULP family of processors represents NXP’s latest achievement
> in ultra-low-power processing for use cases demanding long battery life.
> Targeted towards the growing market of portable devices, the i.MX 7ULP
> family of processors features NXP's advanced implementation of the Arm®
> Cortex®-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D Graphics
> Processing Units (GPUs).
> 
> This patch aims to add the initial support including:
> 1) CLK
> 2) GPIO PTC, PTD, PTE, PTF
> 3) uSDHC 1/2
> 4) LPUART 4/5/6/7
> 5) LPI2C 6/7
> 
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: devicetree@vger.kernel.org
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: Fabio Estevam <fabio.estevam@nxp.com>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
> ChangeLog:
> v1->v2:
>  * update clk part due to binding change
>  * separate soc.dtsi from board.dts
> ---
>  arch/arm/boot/dts/imx7ulp.dtsi | 323 +++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 323 insertions(+)
>  create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi
> 
> diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
> new file mode 100644
> index 0000000..795edc2
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx7ulp.dtsi
> @@ -0,0 +1,323 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> + * Copyright 2017-2018 NXP
> + *   Dong Aisheng <aisheng.dong@nxp.com>
> + */
> +
> +#include <dt-bindings/clock/imx7ulp-clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +#include "imx7ulp-pinfunc.h"
> +
> +/ {
> +	interrupt-parent = <&intc>;
> +
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	aliases {
> +		gpio0 = &gpio_ptc;
> +		gpio1 = &gpio_ptd;
> +		gpio2 = &gpio_pte;
> +		gpio3 = &gpio_ptf;
> +		i2c0 = &lpi2c6;
> +		i2c1 = &lpi2c7;
> +		mmc0 = &usdhc0;
> +		mmc1 = &usdhc1;
> +		serial0 = &lpuart4;
> +		serial1 = &lpuart5;
> +		serial2 = &lpuart6;
> +		serial3 = &lpuart7;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			compatible = "arm,cortex-a7";
> +			device_type = "cpu";
> +			reg = <0>;
> +		};
> +	};
> +
> +	intc: interrupt-controller@40021000 {
> +		compatible = "arm,cortex-a7-gic";
> +		#interrupt-cells = <3>;
> +		interrupt-controller;
> +		reg = <0x40021000 0x1000>,
> +		      <0x40022000 0x1000>;
> +	};
> +
> +	rosc: clock-rosc {
> +		compatible = "fixed-clock";
> +		clock-frequency = <32768>;
> +		clock-output-names = "rosc";
> +		#clock-cells = <0>;
> +	};
> +
> +	sosc: clock-sosc {
> +		compatible = "fixed-clock";
> +		clock-frequency = <24000000>;
> +		clock-output-names = "sosc";
> +		#clock-cells = <0>;
> +	};
> +
> +	sirc: clock-sirc {
> +		compatible = "fixed-clock";
> +		clock-frequency = <16000000>;
> +		clock-output-names = "sirc";
> +		#clock-cells = <0>;
> +	};
> +
> +	firc: clock-firc {
> +		compatible = "fixed-clock";
> +		clock-frequency = <48000000>;
> +		clock-output-names = "firc";
> +		#clock-cells = <0>;
> +	};
> +
> +	upll: clock-upll {
> +		compatible = "fixed-clock";
> +		clock-frequency = <480000000>;
> +		clock-output-names = "upll";
> +		#clock-cells = <0>;
> +	};
> +
> +	mpll: clock-mpll {
> +		compatible = "fixed-clock";
> +		clock-frequency = <480000000>;
> +		clock-output-names = "mpll";
> +		#clock-cells = <0>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv7-timer";
> +		arm,cpu-registers-not-fw-configured;

AIUI, this was a work-around for some existing platform. New platforms 
should not have this property.

> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> +		clock-frequency = <1000000>;

This too should be initialized by firmware and not in DT IIRC.

> +		status = "disabled";

I think enabled should be the norm.

> +	};
> +
> +	ahbbridge0: bus@40000000 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0x40000000 0x800000>;
> +		ranges;
> +
> +		lpuart4: serial@402d0000 {
> +			compatible = "fsl,imx7ulp-lpuart";
> +			reg = <0x402d0000 0x1000>;
> +			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
> +			clock-names = "ipg";
> +			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
> +			assigned-clock-rates = <24000000>;
> +			status = "disabled";
> +		};
> +
> +		lpuart5: serial@402e0000 {
> +			compatible = "fsl,imx7ulp-lpuart";
> +			reg = <0x402e0000 0x1000>;
> +			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
> +			clock-names = "ipg";
> +			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
> +			assigned-clock-rates = <48000000>;
> +			status = "disabled";
> +		};
> +
> +		tpm5: tpm@40260000 {
> +			compatible = "fsl,imx7ulp-tpm";
> +			reg = <0x40260000 0x1000>;
> +			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
> +				 <&pcc2 IMX7ULP_CLK_LPTPM5>;
> +			clock-names = "ipg", "per";
> +		};
> +
> +		usdhc0: usdhc@40370000 {

mmc@... is the standard name.

> +			compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
> +			reg = <0x40370000 0x10000>;
> +			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
> +				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
> +				 <&pcc2 IMX7ULP_CLK_USDHC0>;
> +			clock-names ="ipg", "ahb", "per";
> +			assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
> +			bus-width = <4>;
> +			fsl,tuning-start-tap = <20>;
> +			fsl,tuning-step= <2>;
> +			status = "disabled";
> +		};
> +
> +		usdhc1: usdhc@40380000 {

ditto.

> +			compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
> +			reg = <0x40380000 0x10000>;
> +			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
> +				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
> +				 <&pcc2 IMX7ULP_CLK_USDHC1>;
> +			clock-names ="ipg", "ahb", "per";
> +			assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
> +			bus-width = <4>;
> +			fsl,tuning-start-tap = <20>;
> +			fsl,tuning-step= <2>;
> +			status = "disabled";
> +		};
> +
> +		scg1: scg1@403e0000 {

clock-controller@...

> +			compatible = "fsl,imx7ulp-scg1";
> +			reg = <0x403e0000 0x10000>;
> +			clocks = <&rosc>, <&sosc>, <&sirc>,
> +				 <&firc>, <&upll>, <&mpll>;
> +			clock-names = "rosc", "sosc", "sirc",
> +				      "firc", "upll", "mpll";
> +			#clock-cells = <1>;
> +		};
> +
> +		pcc2: pcc2@403f0000 {

clock-controller@...

> +			compatible = "fsl,imx7ulp-pcc2";
> +			reg = <0x403f0000 0x10000>;
> +			#clock-cells = <1>;
> +			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
> +		};
> +
> +		smc1: smc1@40410000 {
> +			compatible = "fsl,imx7ulp-smc1";
> +			reg = <0x40410000 0x1000>;
> +		};
> +
> +		pcc3: pcc3@40b30000 {

clock-controller@...

> +			compatible = "fsl,imx7ulp-pcc3";
> +			reg = <0x40b30000 0x10000>;
> +			#clock-cells = <1>;
> +		};
> +	};
> +
> +	ahbbridge1: bus@40800000 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0x40800000 0x800000>;
> +		ranges;
> +
> +		lpi2c6: lpi2c@40a40000 {

i2c@...

> +			compatible = "fsl,imx7ulp-lpi2c";
> +			reg = <0x40a40000 0x10000>;
> +			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
> +			clock-names = "ipg";
> +			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
> +			assigned-clock-rates = <48000000>;
> +			status = "disabled";
> +		};
> +
> +		lpi2c7: lpi2c@40a50000 {

i2c@...

> +			compatible = "fsl,imx7ulp-lpi2c";
> +			reg = <0x40a50000 0x10000>;
> +			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
> +			clock-names = "ipg";
> +			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
> +			assigned-clock-rates = <48000000>;
> +			status = "disabled";
> +		};
> +
> +		lpuart6: serial@40a60000 {
> +			compatible = "fsl,imx7ulp-lpuart";
> +			reg = <0x40a60000 0x1000>;
> +			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
> +			clock-names = "ipg";
> +			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
> +			assigned-clock-rates = <48000000>;
> +			status = "disabled";
> +		};
> +
> +		lpuart7: serial@40a70000 {
> +			compatible = "fsl,imx7ulp-lpuart";
> +			reg = <0x40a70000 0x1000>;
> +			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pcc3  IMX7ULP_CLK_LPUART7>;
> +			clock-names = "ipg";
> +			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
> +			assigned-clock-rates = <48000000>;
> +			status = "disabled";
> +		};
> +
> +		iomuxc1: iomuxc@40ac0000 {

pinctrl@...

> +			compatible = "fsl,imx7ulp-iomuxc1";
> +			reg = <0x40ac0000 0x1000>;
> +		};
> +
> +		gpio_ptc: gpio@40ae0000 {
> +			compatible = "fsl,vf610-gpio";
> +			reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
> +				 <&pcc3 IMX7ULP_CLK_PCTLC>;
> +			clock-names = "gpio", "port";
> +			gpio-ranges = <&iomuxc1 0 0 32>;
> +		};
> +
> +		gpio_ptd: gpio@40af0000 {
> +			compatible = "fsl,vf610-gpio";
> +			reg = <0x40af0000 0x1000 0x400f0040 0x40>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
> +				 <&pcc3 IMX7ULP_CLK_PCTLD>;
> +			clock-names = "gpio", "port";
> +			gpio-ranges = <&iomuxc1 0 32 32>;
> +		};
> +
> +		gpio_pte: gpio@40b00000 {
> +			compatible = "fsl,vf610-gpio";
> +			reg = <0x40b00000 0x1000 0x400f0080 0x40>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
> +				 <&pcc3 IMX7ULP_CLK_PCTLE>;
> +			clock-names = "gpio", "port";
> +			gpio-ranges = <&iomuxc1 0 64 32>;
> +		};
> +
> +		gpio_ptf: gpio@40b10000 {
> +			compatible = "fsl,vf610-gpio";
> +			reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
> +				 <&pcc3 IMX7ULP_CLK_PCTLF>;
> +			clock-names = "gpio", "port";
> +			gpio-ranges = <&iomuxc1 0 96 32>;
> +		};
> +	};
> +};
> -- 
> 2.7.4
> 

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RE: [PATCH V2 6/8] dts: imx: add common imx7ulp dtsi support

[A.s. Dong]

> -----Original Message-----
> From: Rob Herring [mailto:robh@kernel.org]
> Sent: Thursday, October 25, 2018 6:02 AM
[...]
> On Tue, Oct 23, 2018 at 11:49:25AM +0000, A.s. Dong wrote:
> > The i.MX 7ULP family of processors represents NXP’s latest achievement
> > in ultra-low-power processing for use cases demanding long battery life.
> > Targeted towards the growing market of portable devices, the i.MX 7ULP
> > family of processors features NXP's advanced implementation of the
> > Arm®
> > Cortex®-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D
> > Graphics Processing Units (GPUs).
> >
> > This patch aims to add the initial support including:
> > 1) CLK
> > 2) GPIO PTC, PTD, PTE, PTF
> > 3) uSDHC 1/2
> > 4) LPUART 4/5/6/7
> > 5) LPI2C 6/7
> >
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: Shawn Guo <shawnguo@kernel.org>
> > Cc: devicetree@vger.kernel.org
> > Cc: Sascha Hauer <kernel@pengutronix.de>
> > Cc: Fabio Estevam <fabio.estevam@nxp.com>
> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> > ---
> > ChangeLog:
> > v1->v2:
> >  * update clk part due to binding change
> >  * separate soc.dtsi from board.dts
> > ---
> >  arch/arm/boot/dts/imx7ulp.dtsi | 323
> > +++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 323 insertions(+)
> >  create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi
> >
> > diff --git a/arch/arm/boot/dts/imx7ulp.dtsi
> > b/arch/arm/boot/dts/imx7ulp.dtsi new file mode 100644 index
> > 0000000..795edc2
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/imx7ulp.dtsi
> > @@ -0,0 +1,323 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> > + * Copyright 2017-2018 NXP
> > + *   Dong Aisheng <aisheng.dong@nxp.com>
> > + */
> > +
> > +#include <dt-bindings/clock/imx7ulp-clock.h>
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +#include "imx7ulp-pinfunc.h"
> > +
> > +/ {
> > +	interrupt-parent = <&intc>;
> > +
> > +	#address-cells = <1>;
> > +	#size-cells = <1>;
> > +
> > +	aliases {
> > +		gpio0 = &gpio_ptc;
> > +		gpio1 = &gpio_ptd;
> > +		gpio2 = &gpio_pte;
> > +		gpio3 = &gpio_ptf;
> > +		i2c0 = &lpi2c6;
> > +		i2c1 = &lpi2c7;
> > +		mmc0 = &usdhc0;
> > +		mmc1 = &usdhc1;
> > +		serial0 = &lpuart4;
> > +		serial1 = &lpuart5;
> > +		serial2 = &lpuart6;
> > +		serial3 = &lpuart7;
> > +	};
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		cpu0: cpu@0 {
> > +			compatible = "arm,cortex-a7";
> > +			device_type = "cpu";
> > +			reg = <0>;
> > +		};
> > +	};
> > +
> > +	intc: interrupt-controller@40021000 {
> > +		compatible = "arm,cortex-a7-gic";
> > +		#interrupt-cells = <3>;
> > +		interrupt-controller;
> > +		reg = <0x40021000 0x1000>,
> > +		      <0x40022000 0x1000>;
> > +	};
> > +
> > +	rosc: clock-rosc {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <32768>;
> > +		clock-output-names = "rosc";
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	sosc: clock-sosc {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <24000000>;
> > +		clock-output-names = "sosc";
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	sirc: clock-sirc {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <16000000>;
> > +		clock-output-names = "sirc";
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	firc: clock-firc {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <48000000>;
> > +		clock-output-names = "firc";
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	upll: clock-upll {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <480000000>;
> > +		clock-output-names = "upll";
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	mpll: clock-mpll {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <480000000>;
> > +		clock-output-names = "mpll";
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	timer {
> > +		compatible = "arm,armv7-timer";
> > +		arm,cpu-registers-not-fw-configured;
> 
> AIUI, this was a work-around for some existing platform. New platforms should
> not have this property.
> 
> > +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_LOW)>;
> > +		clock-frequency = <1000000>;
> 
> This too should be initialized by firmware and not in DT IIRC.
> 

Sorry for the careless. I should double checking these codes before sending
as the origin code base is quite old since first version.


> > +		status = "disabled";
> 
> I think enabled should be the norm.
> 

This is mostly because the arm timer may stop during low power idle
and we already have a TPM timer function the same in SoC.
Do you think we should still enable it?

> > +	};
> > +
> > +	ahbbridge0: bus@40000000 {
> > +		compatible = "simple-bus";
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		reg = <0x40000000 0x800000>;
> > +		ranges;
> > +
> > +		lpuart4: serial@402d0000 {
> > +			compatible = "fsl,imx7ulp-lpuart";
> > +			reg = <0x402d0000 0x1000>;
> > +			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> > +			clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
> > +			clock-names = "ipg";
> > +			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
> > +			assigned-clock-parents = <&scg1
> IMX7ULP_CLK_SOSC_BUS_CLK>;
> > +			assigned-clock-rates = <24000000>;
> > +			status = "disabled";
> > +		};
> > +
> > +		lpuart5: serial@402e0000 {
> > +			compatible = "fsl,imx7ulp-lpuart";
> > +			reg = <0x402e0000 0x1000>;
> > +			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> > +			clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
> > +			clock-names = "ipg";
> > +			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
> > +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
> > +			assigned-clock-rates = <48000000>;
> > +			status = "disabled";
> > +		};
> > +
> > +		tpm5: tpm@40260000 {
> > +			compatible = "fsl,imx7ulp-tpm";
> > +			reg = <0x40260000 0x1000>;
> > +			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> > +			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
> > +				 <&pcc2 IMX7ULP_CLK_LPTPM5>;
> > +			clock-names = "ipg", "per";
> > +		};
> > +
> > +		usdhc0: usdhc@40370000 {
> 
> mmc@... is the standard name.
> 

I should be more careful about these. Other places are the same.
Thanks for the reminder.

Regards
Dong Aisheng
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Re: [PATCH V2 6/8] dts: imx: add common imx7ulp dtsi support

[Fabio Estevam]

On Tue, Oct 23, 2018 at 8:55 AM A.s. Dong <aisheng.dong@nxp.com> wrote:

> +               gpio_ptc: gpio@40ae0000 {
> +                       compatible = "fsl,vf610-gpio";

This should be:

compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";

RE: [PATCH V2 6/8] dts: imx: add common imx7ulp dtsi support

[A.s. Dong]

> -----Original Message-----
> From: Fabio Estevam [mailto:festevam@gmail.com]
> Sent: Friday, October 26, 2018 12:44 AM
[...]
> On Tue, Oct 23, 2018 at 8:55 AM A.s. Dong <aisheng.dong@nxp.com> wrote:
> 
> > +               gpio_ptc: gpio@40ae0000 {
> > +                       compatible = "fsl,vf610-gpio";
> 
> This should be:
> 
> compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";

That's true.
Thanks for reminder.

Regards
Dong Aisheng

[PATCH V2 7/8] dts: fsl: add imx7ulp evk support

[A.s. Dong]

The NXP i.MX 7ULP Evaluation Kit (EVK) provides a platform for rapid
evaluation of the i.MX 7ULP, which features NXP's advanced implementation
of the Arm® Cortex®-A7 core, the Arm Cortex-M4 core, as well as a 3D and
2D Graphics Processing Units (GPUs).

The EVK enables HDMI output for simple out-of-the-box to bring up but
allows reconfiguration for MIPI displays. The EVK is designed as a
System-On-Module(SOM) board that connects to an associated baseboard.
The SOM provides 1 GB LPDDR3, 8 MB Quad SPI flash, Micro SD 3.0 card
socket, WiFi/ Bluetooth capability, USB 2.0 OTG with Type C connector
and an NXP PF1550 power management IC (PMIC). The baseboard provides
additional capabilities including a full SD/MMC 3.0 card socket, audio
codec, multiple sensors, an HDMI connector, and an alternate MIPI display
connector. Additionally, the EVK facilitates software development with the
ultimate goal of faster time to market through the support of both
Linux® OS and AndroidTM rich operating systems, as well as FreeRTOS.

This patch aims to support the preliminary booting up features
as follows:
GPIO
LPUART
FEC
SD/MMC

See more board details:
https://www.nxp.com/products/processors-and-microcontrollers/
arm-based-processors-and-mcus/i.mx-applications-processors/
i.mx-7-processors/evaluation-kit-for-the-i.mx-7ulp-applications
-processor:MCIMX7ULP-EVK

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v1->v2:
 * switch to SPDX license
 * pad name update
 * fix Character '_' not recommended in node name
 * separate from soc.dtsi file
---
 arch/arm/boot/dts/Makefile        |  2 +
 arch/arm/boot/dts/imx7ulp-evk.dts | 94 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 96 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx7ulp-evk.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d7268ae..39eac9c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -573,6 +573,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
 	imx7d-sdb-sht11.dtb \
 	imx7s-colibri-eval-v3.dtb \
 	imx7s-warp.dtb
+dtb-$(CONFIG_SOC_IMX7ULP) += \
+	imx7ulp-evk.dtb
 dtb-$(CONFIG_SOC_LS1021A) += \
 	ls1021a-moxa-uc-8410a.dtb \
 	ls1021a-qds.dtb \
diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts
new file mode 100644
index 0000000..d876cb3
--- /dev/null
+++ b/arch/arm/boot/dts/imx7ulp-evk.dts
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *   Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+/dts-v1/;
+
+#include "imx7ulp.dtsi"
+
+/ {
+	model = "NXP i.MX7ULP EVK";
+	compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system";
+
+	chosen {
+		stdout-path = &lpuart4;
+	};
+
+	memory@60000000 {
+		reg = <0x60000000 0x40000000>;
+	};
+
+	reg_vsd_3v3: regulator-vsd-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usdhc0_rst>;
+		gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&lpuart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart4>;
+	status = "okay";
+};
+
+&usdhc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc0_cmd_data>, <&pinctrl_usdhc0_clk>,
+		    <&pinctrl_usdhc0_cd>;
+	cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_vsd_3v3>;
+	status = "okay";
+};
+
+&iomuxc1 {
+	pinctrl_lpuart4: lpuart4grp {
+		pinmux = <
+			IMX7ULP_PAD_PTC3__LPUART4_RX
+			IMX7ULP_PAD_PTC2__LPUART4_TX
+		>;
+		bias-pull-up;
+	};
+
+	pinctrl_usdhc0_cmd_data: usdhc0-cmd-data-grp {
+		pinmux = <
+			IMX7ULP_PAD_PTD1__SDHC0_CMD
+			IMX7ULP_PAD_PTD2__SDHC0_CLK
+			IMX7ULP_PAD_PTD7__SDHC0_D3
+			IMX7ULP_PAD_PTD8__SDHC0_D2
+			IMX7ULP_PAD_PTD9__SDHC0_D1
+			IMX7ULP_PAD_PTD10__SDHC0_D0
+		>;
+		drive-strength = <1>;
+		bias-pull-up;
+	};
+
+	pinctrl_usdhc0_clk: usdhc0-clk-grp {
+		pinmux = <
+			IMX7ULP_PAD_PTD2__SDHC0_CLK
+		>;
+		drive-strength = <1>;
+		bias-pull-down;
+	};
+
+	pinctrl_usdhc0_cd: usdhc0-gpio-cd-grp {
+		pinmux = <
+			IMX7ULP_PAD_PTC10__PTC10	/* USDHC0 CD */
+		>;
+		bias-pull-up;
+	};
+
+	pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp {
+		pinmux = <
+			IMX7ULP_PAD_PTD0__PTD0		/* USDHC0 RST */
+		>;
+		bias-pull-up;
+	};
+};
-- 
2.7.4

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Re: [PATCH V2 7/8] dts: fsl: add imx7ulp evk support

[Fabio Estevam]

On Tue, Oct 23, 2018 at 8:56 AM A.s. Dong <aisheng.dong@nxp.com> wrote:

> +/ {
> +       model = "NXP i.MX7ULP EVK";
> +       compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system";

This "Generic DT based system" should be removed.

> +       chosen {
> +               stdout-path = &lpuart4;
> +       };
> +
> +       memory@60000000 {

       device_type = "memory";
> +               reg = <0x60000000 0x40000000>;
> +       };

> +&iomuxc1 {
> +       pinctrl_lpuart4: lpuart4grp {
> +               pinmux = <
> +                       IMX7ULP_PAD_PTC3__LPUART4_RX
> +                       IMX7ULP_PAD_PTC2__LPUART4_TX
> +               >;
> +               bias-pull-up;

Please change the mx7ulp pinctrl driver to accept the "old" notation
and change the dts to use:

IMX7ULP_PAD_PTC3__LPUART4_RX 0x3

This way we use the same method for all i.MX devices.

RE: [PATCH V2 7/8] dts: fsl: add imx7ulp evk support

[A.s. Dong]

> -----Original Message-----
> From: Fabio Estevam [mailto:festevam@gmail.com]
> Sent: Tuesday, October 23, 2018 8:29 PM
[...] 
> On Tue, Oct 23, 2018 at 8:56 AM A.s. Dong <aisheng.dong@nxp.com> wrote:
> 
> > +/ {
> > +       model = "NXP i.MX7ULP EVK";
> > +       compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT
> > +based system";
> 
> This "Generic DT based system" should be removed.
> 

Got it

> > +       chosen {
> > +               stdout-path = &lpuart4;
> > +       };
> > +
> > +       memory@60000000 {
> 
>        device_type = "memory";

Got it

> > +               reg = <0x60000000 0x40000000>;
> > +       };
> 
> > +&iomuxc1 {
> > +       pinctrl_lpuart4: lpuart4grp {
> > +               pinmux = <
> > +                       IMX7ULP_PAD_PTC3__LPUART4_RX
> > +                       IMX7ULP_PAD_PTC2__LPUART4_TX
> > +               >;
> > +               bias-pull-up;
> 
> Please change the mx7ulp pinctrl driver to accept the "old" notation and
> change the dts to use:
> 
> IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
> 
> This way we use the same method for all i.MX devices.

I'm a bit hesitate to do that as the driver already supports it. There's no extra effort
to use it. And we probably could take ULP as a special case to test generic binding
rather then simply drop it and drop driver features. Once we get objection from users
later, we still can simply fallback as there's still only official boards using it.

Last, it's not correct that there's not only one method for all i.MX devices.
MX23/28 are different ones and ULP is more like MX23/28.
And I saw no objections from users for MX23/28.

Regards
Dong Aisheng

Re: [PATCH V2 7/8] dts: fsl: add imx7ulp evk support

[Fabio Estevam]

On Tue, Oct 23, 2018 at 11:42 AM A.s. Dong <aisheng.dong@nxp.com> wrote:

> I'm a bit hesitate to do that as the driver already supports it. There's no extra effort
> to use it. And we probably could take ULP as a special case to test generic binding
> rather then simply drop it and drop driver features. Once we get objection from users
> later, we still can simply fallback as there's still only official boards using it.

We had this same discussion some months ago when we were reviewing
i.MX8 support.

I don't see the value in doing pinctrl differently on i.MX7ULP.

> Last, it's not correct that there's not only one method for all i.MX devices.
> MX23/28 are different ones and ULP is more like MX23/28.
> And I saw no objections from users for MX23/28.

Yes, but these are legacy platforms.

For new ones, we should try to keep consistency, just like we
discussed during i.MX8 review.

RE: [PATCH V2 7/8] dts: fsl: add imx7ulp evk support

[A.s. Dong]

> -----Original Message-----
> From: Fabio Estevam [mailto:festevam@gmail.com]
> Sent: Wednesday, October 24, 2018 12:26 AM
[...]
> On Tue, Oct 23, 2018 at 11:42 AM A.s. Dong <aisheng.dong@nxp.com> wrote:
> 
> > I'm a bit hesitate to do that as the driver already supports it.
> > There's no extra effort to use it. And we probably could take ULP as a
> > special case to test generic binding rather then simply drop it and
> > drop driver features. Once we get objection from users later, we still can
> simply fallback as there's still only official boards using it.
> 
> We had this same discussion some months ago when we were reviewing
> i.MX8 support.
>
> I don't see the value in doing pinctrl differently on i.MX7ULP.
>

I thought the situation is different as ULP actually already supports generic binding
before that discussion.

> > Last, it's not correct that there's not only one method for all i.MX devices.
> > MX23/28 are different ones and ULP is more like MX23/28.
> > And I saw no objections from users for MX23/28.
> 
> Yes, but these are legacy platforms.
> 
> For new ones, we should try to keep consistency, just like we discussed during
> i.MX8 review.

So the question is whether it's necessary to switch generic binding back to the
legacy one for ULP. Personally I'm not strongly against this, but I need some
confirmation from Shawn and Sascha.

Shawn & Sascha, would you make a judgement call?
If you also strongly request that, I will try to make it patch to test Linus W.
Hopefully our agreement could satisfy Linus W.

Regards
Dong Aisheng

RE: [PATCH V2 7/8] dts: fsl: add imx7ulp evk support

[A.s. Dong]

Hi Shawn & Sascha,

> -----Original Message-----
> From: A.s. Dong
> Sent: Wednesday, October 24, 2018 4:14 PM
[...]
> > -----Original Message-----
> > From: Fabio Estevam [mailto:festevam@gmail.com]
> > Sent: Wednesday, October 24, 2018 12:26 AM
> [...]
> > On Tue, Oct 23, 2018 at 11:42 AM A.s. Dong <aisheng.dong@nxp.com>
> wrote:
> >
> > > I'm a bit hesitate to do that as the driver already supports it.
> > > There's no extra effort to use it. And we probably could take ULP as
> > > a special case to test generic binding rather then simply drop it
> > > and drop driver features. Once we get objection from users later, we
> > > still can
> > simply fallback as there's still only official boards using it.
> >
> > We had this same discussion some months ago when we were reviewing
> > i.MX8 support.
> >
> > I don't see the value in doing pinctrl differently on i.MX7ULP.
> >
> 
> I thought the situation is different as ULP actually already supports generic
> binding before that discussion.
> 
> > > Last, it's not correct that there's not only one method for all i.MX devices.
> > > MX23/28 are different ones and ULP is more like MX23/28.
> > > And I saw no objections from users for MX23/28.
> >
> > Yes, but these are legacy platforms.
> >
> > For new ones, we should try to keep consistency, just like we
> > discussed during
> > i.MX8 review.
> 
> So the question is whether it's necessary to switch generic binding back to the
> legacy one for ULP. Personally I'm not strongly against this, but I need some
> confirmation from Shawn and Sascha.
> 
> Shawn & Sascha, would you make a judgement call?
> If you also strongly request that, I will try to make it patch to test Linus W.
> Hopefully our agreement could satisfy Linus W.
> 

Would you please let me know if you're all okay with this?

Regards
Dong Aisheng

> Regards
> Dong Aisheng

Re: [PATCH V2 7/8] dts: fsl: add imx7ulp evk support

[Sascha Hauer]

On Wed, Oct 24, 2018 at 08:14:01AM +0000, A.s. Dong wrote:
> > -----Original Message-----
> > From: Fabio Estevam [mailto:festevam@gmail.com]
> > Sent: Wednesday, October 24, 2018 12:26 AM
> [...]
> > On Tue, Oct 23, 2018 at 11:42 AM A.s. Dong <aisheng.dong@nxp.com> wrote:
> > 
> > > I'm a bit hesitate to do that as the driver already supports it.
> > > There's no extra effort to use it. And we probably could take ULP as a
> > > special case to test generic binding rather then simply drop it and
> > > drop driver features. Once we get objection from users later, we still can
> > simply fallback as there's still only official boards using it.
> > 
> > We had this same discussion some months ago when we were reviewing
> > i.MX8 support.
> >
> > I don't see the value in doing pinctrl differently on i.MX7ULP.
> >
> 
> I thought the situation is different as ULP actually already supports generic binding
> before that discussion.
> 
> > > Last, it's not correct that there's not only one method for all i.MX devices.
> > > MX23/28 are different ones and ULP is more like MX23/28.
> > > And I saw no objections from users for MX23/28.
> > 
> > Yes, but these are legacy platforms.
> > 
> > For new ones, we should try to keep consistency, just like we discussed during
> > i.MX8 review.
> 
> So the question is whether it's necessary to switch generic binding back to the
> legacy one for ULP. Personally I'm not strongly against this, but I need some
> confirmation from Shawn and Sascha.
> 
> Shawn & Sascha, would you make a judgement call?
> If you also strongly request that, I will try to make it patch to test Linus W.
> Hopefully our agreement could satisfy Linus W.

For consistency reasons I vote for using the legacy binding for i.MX7ulp
aswell.

Sascha

-- 
Pengutronix e.K.                           |                             |
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RE: [PATCH V2 7/8] dts: fsl: add imx7ulp evk support

[A.s. Dong]

> -----Original Message-----
> From: Sascha Hauer [mailto:s.hauer@pengutronix.de]
> Sent: Friday, October 26, 2018 6:57 PM
[...]
> 
> On Wed, Oct 24, 2018 at 08:14:01AM +0000, A.s. Dong wrote:
> > > -----Original Message-----
> > > From: Fabio Estevam [mailto:festevam@gmail.com]
> > > Sent: Wednesday, October 24, 2018 12:26 AM
> > [...]
> > > On Tue, Oct 23, 2018 at 11:42 AM A.s. Dong <aisheng.dong@nxp.com>
> wrote:
> > >
> > > > I'm a bit hesitate to do that as the driver already supports it.
> > > > There's no extra effort to use it. And we probably could take ULP
> > > > as a special case to test generic binding rather then simply drop
> > > > it and drop driver features. Once we get objection from users
> > > > later, we still can
> > > simply fallback as there's still only official boards using it.
> > >
> > > We had this same discussion some months ago when we were reviewing
> > > i.MX8 support.
> > >
> > > I don't see the value in doing pinctrl differently on i.MX7ULP.
> > >
> >
> > I thought the situation is different as ULP actually already supports
> > generic binding before that discussion.
> >
> > > > Last, it's not correct that there's not only one method for all i.MX devices.
> > > > MX23/28 are different ones and ULP is more like MX23/28.
> > > > And I saw no objections from users for MX23/28.
> > >
> > > Yes, but these are legacy platforms.
> > >
> > > For new ones, we should try to keep consistency, just like we
> > > discussed during
> > > i.MX8 review.
> >
> > So the question is whether it's necessary to switch generic binding
> > back to the legacy one for ULP. Personally I'm not strongly against
> > this, but I need some confirmation from Shawn and Sascha.
> >
> > Shawn & Sascha, would you make a judgement call?
> > If you also strongly request that, I will try to make it patch to test Linus W.
> > Hopefully our agreement could satisfy Linus W.
> 
> For consistency reasons I vote for using the legacy binding for i.MX7ulp aswell.
> 

Thanks for the feedback.
Will try to cook a patch to send to Linus W.

Regards
Dong Aisheng

> Sascha
> 
> --
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