* Re: [PATCH v5 5/8] ARM: l2x0: add marvell,ecc-enable property for aurora
2018-10-29 7:25 ` [PATCH v5 5/8] ARM: l2x0: add marvell,ecc-enable property for aurora Chris Packham
@ 2018-10-30 19:31 ` Rob Herring
2018-11-08 15:17 ` Borislav Petkov
1 sibling, 0 replies; 3+ messages in thread
From: Rob Herring @ 2018-10-30 19:31 UTC (permalink / raw)
Cc: linux, u.kleine-koenig, jlu, bp, linux-arm-kernel, linux-edac,
linux-kernel, Chris Packham, Mark Rutland, devicetree
On Mon, 29 Oct 2018 20:25:32 +1300, Chris Packham wrote:
> The aurora cache on the Marvell Armada-XP SoC supports ECC protection
> for the L2 data arrays. Add a "marvell,ecc-enable" device tree property
> which can be used to enable this.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> [jlu@pengutronix.de: use aurora specific define AURORA_ACR_ECC_EN]
> Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
> ---
> Documentation/devicetree/bindings/arm/l2c2x0.txt | 2 ++
> arch/arm/mm/cache-l2x0.c | 7 +++++++
> 2 files changed, 9 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v5 5/8] ARM: l2x0: add marvell,ecc-enable property for aurora
2018-10-29 7:25 ` [PATCH v5 5/8] ARM: l2x0: add marvell,ecc-enable property for aurora Chris Packham
2018-10-30 19:31 ` Rob Herring
@ 2018-11-08 15:17 ` Borislav Petkov
1 sibling, 0 replies; 3+ messages in thread
From: Borislav Petkov @ 2018-11-08 15:17 UTC (permalink / raw)
To: Chris Packham
Cc: linux, u.kleine-koenig, jlu, linux-arm-kernel, linux-edac,
linux-kernel, Rob Herring, Mark Rutland, devicetree
On Mon, Oct 29, 2018 at 08:25:32PM +1300, Chris Packham wrote:
> The aurora cache on the Marvell Armada-XP SoC supports ECC protection
> for the L2 data arrays. Add a "marvell,ecc-enable" device tree property
> which can be used to enable this.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> [jlu@pengutronix.de: use aurora specific define AURORA_ACR_ECC_EN]
> Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
> ---
> Documentation/devicetree/bindings/arm/l2c2x0.txt | 2 ++
> arch/arm/mm/cache-l2x0.c | 7 +++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt
> index fbe6cb21f4cf..15a84f0ba9f1 100644
> --- a/Documentation/devicetree/bindings/arm/l2c2x0.txt
> +++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt
> @@ -76,6 +76,8 @@ Optional properties:
> specified to indicate that such transforms are precluded.
> - arm,parity-enable : enable parity checking on the L2 cache (L220 or PL310).
> - arm,parity-disable : disable parity checking on the L2 cache (L220 or PL310).
> +- marvell,ecc-enable : enable ECC protection on the L2 cache
> +- marvell,ecc-disable : disable ECC protection on the L2 cache
> - arm,outer-sync-disable : disable the outer sync operation on the L2 cache.
> Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
> will randomly hang unless outer sync operations are disabled.
> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> index b70bee74750d..644f786e4fa9 100644
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -1505,6 +1505,13 @@ static void __init aurora_of_parse(const struct device_node *np,
> mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
> }
>
> + if (of_property_read_bool(np, "marvell,ecc-enable")) {
> + mask |= AURORA_ACR_ECC_EN;
> + val |= AURORA_ACR_ECC_EN;
> + } else if (of_property_read_bool(np, "marvell,ecc-disable")) {
> + mask |= AURORA_ACR_ECC_EN;
> + }
> +
> if (of_property_read_bool(np, "arm,parity-enable")) {
> mask |= AURORA_ACR_PARITY_EN;
> val |= AURORA_ACR_PARITY_EN;
> --
checkpatch complains here:
WARNING: DT binding docs and includes should be a separate patch. See: Documentation/devicetree/bindings/submitting-patches.txt
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
^ permalink raw reply [flat|nested] 3+ messages in thread