From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shawn Guo Subject: Re: [PATCH v7 5/6] arm64: dts: add QorIQ LX2160A SoC support Date: Wed, 31 Oct 2018 14:25:14 +0800 Message-ID: <20181031062513.GC10386@tiger> References: <1540759926-3641-1-git-send-email-vabhav.sharma@nxp.com> <1540759926-3641-6-git-send-email-vabhav.sharma@nxp.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <1540759926-3641-6-git-send-email-vabhav.sharma@nxp.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Vabhav Sharma Cc: "mark.rutland@arm.com" , "kstewart@linuxfoundation.org" , "ulf.hansson@linaro.org" , Yogesh Narayan Gaur , "linux-kernel-owner@vger.kernel.org" , "catalin.marinas@arm.com" , "mturquette@baylibre.com" , "will.deacon@arm.com" , "adrian.hunter@intel.com" , "yamada.masahiro@socionext.com" , Sriram Dash , "linux-clk@vger.kernel.org" , Horia Geanta , Pankaj Bansal , Udit Kumar , "linux@armlinux.org.uk" , Priyanka Jain , "viresh.kumar@linaro.org" List-Id: devicetree@vger.kernel.org On Mon, Oct 29, 2018 at 08:57:54AM +0000, Vabhav Sharma wrote: > LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture. > > LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor cores > in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8 I2C > controllers, 3 dspi, 2 esdhc,2 USB 3.0, mmu 500, 3 SATA, 4 PL011 SBSA > UARTs etc. > > Signed-off-by: Ramneek Mehresh > Signed-off-by: Zhang Ying-22455 > Signed-off-by: Nipun Gupta > Signed-off-by: Priyanka Jain > Signed-off-by: Yogesh Gaur > Signed-off-by: Sriram Dash > Signed-off-by: Vabhav Sharma > Signed-off-by: Horia Geanta > Signed-off-by: Ran Wang > Signed-off-by: Yinbo Zhu Applied, thanks.