[PATCH 1/7] clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width

[PATCH 1/7] clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width

[Jagan Teki]

MUX bits for MMC clock register range are 25:24 where 24 is shift
and 2 is width So fix the width number from 3 to 2.

Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
index 2193e1495086..e2bc612f1d3e 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
@@ -411,7 +411,7 @@ static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x",
 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830,
 					  0, 4,		/* M */
 					  8, 2,		/* N */
-					  24, 3,	/* mux */
+					  24, 2,	/* mux */
 					  BIT(31),	/* gate */
 					  2,		/* post-div */
 					  0);
@@ -419,7 +419,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830,
 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834,
 					  0, 4,		/* M */
 					  8, 2,		/* N */
-					  24, 3,	/* mux */
+					  24, 2,	/* mux */
 					  BIT(31),	/* gate */
 					  2,		/* post-div */
 					  0);
@@ -427,7 +427,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834,
 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838,
 					  0, 4,		/* M */
 					  8, 2,		/* N */
-					  24, 3,	/* mux */
+					  24, 2,	/* mux */
 					  BIT(31),	/* gate */
 					  2,		/* post-div */
 					  0);
-- 
2.18.0.321.gffc6fa0e3

[PATCH 2/7] arm64: allwinner: h6: Add common orangepi nodes into dtsi

[Jagan Teki]

Orangepi H6 boards, One Plus and Lite2 shares common
nodes like axp805, uart, mmc0 etc and the common differences
between them is Ethernet is available in One Plus where
as Wifi, USB3, CSI port is available in Lite2.

So, add common orangepi nodes into sun50i-h6-orangepi.dtsi

Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
 .../allwinner/sun50i-h6-orangepi-one-plus.dts | 140 +---------------
 .../dts/allwinner/sun50i-h6-orangepi.dtsi     | 150 ++++++++++++++++++
 2 files changed, 151 insertions(+), 139 deletions(-)
 create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
index 0612c19cd994..12e17567ab56 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
@@ -4,147 +4,9 @@
  * Author: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
  */
 
-/dts-v1/;
-
-#include "sun50i-h6.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
+#include "sun50i-h6-orangepi.dtsi"
 
 / {
 	model = "OrangePi One Plus";
 	compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-};
-
-&mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins>;
-	vmmc-supply = <&reg_cldo1>;
-	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
-	bus-width = <4>;
-	status = "okay";
-};
-
-&r_i2c {
-	status = "okay";
-
-	axp805: pmic@36 {
-		compatible = "x-powers,axp805", "x-powers,axp806";
-		reg = <0x36>;
-		interrupt-parent = <&r_intc>;
-		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-		interrupt-controller;
-		#interrupt-cells = <1>;
-		x-powers,self-working-mode;
-
-		regulators {
-			reg_aldo1: aldo1 {
-				regulator-always-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-name = "vcc-pl";
-			};
-
-			reg_aldo2: aldo2 {
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-name = "vcc-ac200";
-			};
-
-			reg_aldo3: aldo3 {
-				regulator-always-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-name = "vcc25-dram";
-			};
-
-			reg_bldo1: bldo1 {
-				regulator-always-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-name = "vcc-bias-pll";
-			};
-
-			reg_bldo2: bldo2 {
-				regulator-always-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-name = "vcc-efuse-pcie-hdmi-io";
-			};
-
-			reg_bldo3: bldo3 {
-				regulator-always-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-name = "vcc-dcxoio";
-			};
-
-			bldo4 {
-				/* unused */
-			};
-
-			reg_cldo1: cldo1 {
-				regulator-always-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-name = "vcc-3v3";
-			};
-
-			reg_cldo2: cldo2 {
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-name = "vcc-wifi-1";
-			};
-
-			reg_cldo3: cldo3 {
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-name = "vcc-wifi-2";
-			};
-
-			reg_dcdca: dcdca {
-				regulator-always-on;
-				regulator-min-microvolt = <810000>;
-				regulator-max-microvolt = <1080000>;
-				regulator-name = "vdd-cpu";
-			};
-
-			reg_dcdcc: dcdcc {
-				regulator-min-microvolt = <810000>;
-				regulator-max-microvolt = <1080000>;
-				regulator-name = "vdd-gpu";
-			};
-
-			reg_dcdcd: dcdcd {
-				regulator-always-on;
-				regulator-min-microvolt = <960000>;
-				regulator-max-microvolt = <960000>;
-				regulator-name = "vdd-sys";
-			};
-
-			reg_dcdce: dcdce {
-				regulator-always-on;
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <1200000>;
-				regulator-name = "vcc-dram";
-			};
-
-			sw {
-				/* unused */
-			};
-		};
-	};
-};
-
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_ph_pins>;
-	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
new file mode 100644
index 000000000000..0612c19cd994
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions
+ * Author: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
+ */
+
+/dts-v1/;
+
+#include "sun50i-h6.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "OrangePi One Plus";
+	compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins>;
+	vmmc-supply = <&reg_cldo1>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+	bus-width = <4>;
+	status = "okay";
+};
+
+&r_i2c {
+	status = "okay";
+
+	axp805: pmic@36 {
+		compatible = "x-powers,axp805", "x-powers,axp806";
+		reg = <0x36>;
+		interrupt-parent = <&r_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		x-powers,self-working-mode;
+
+		regulators {
+			reg_aldo1: aldo1 {
+				regulator-always-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc-pl";
+			};
+
+			reg_aldo2: aldo2 {
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc-ac200";
+			};
+
+			reg_aldo3: aldo3 {
+				regulator-always-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc25-dram";
+			};
+
+			reg_bldo1: bldo1 {
+				regulator-always-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc-bias-pll";
+			};
+
+			reg_bldo2: bldo2 {
+				regulator-always-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc-efuse-pcie-hdmi-io";
+			};
+
+			reg_bldo3: bldo3 {
+				regulator-always-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc-dcxoio";
+			};
+
+			bldo4 {
+				/* unused */
+			};
+
+			reg_cldo1: cldo1 {
+				regulator-always-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc-3v3";
+			};
+
+			reg_cldo2: cldo2 {
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc-wifi-1";
+			};
+
+			reg_cldo3: cldo3 {
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc-wifi-2";
+			};
+
+			reg_dcdca: dcdca {
+				regulator-always-on;
+				regulator-min-microvolt = <810000>;
+				regulator-max-microvolt = <1080000>;
+				regulator-name = "vdd-cpu";
+			};
+
+			reg_dcdcc: dcdcc {
+				regulator-min-microvolt = <810000>;
+				regulator-max-microvolt = <1080000>;
+				regulator-name = "vdd-gpu";
+			};
+
+			reg_dcdcd: dcdcd {
+				regulator-always-on;
+				regulator-min-microvolt = <960000>;
+				regulator-max-microvolt = <960000>;
+				regulator-name = "vdd-sys";
+			};
+
+			reg_dcdce: dcdce {
+				regulator-always-on;
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-name = "vcc-dram";
+			};
+
+			sw {
+				/* unused */
+			};
+		};
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_ph_pins>;
+	status = "okay";
+};
-- 
2.18.0.321.gffc6fa0e3

Re: [PATCH 2/7] arm64: allwinner: h6: Add common orangepi nodes into dtsi

[Chen-Yu Tsai]

On Thu, Nov 1, 2018 at 2:37 AM Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> wrote:
>
> Orangepi H6 boards, One Plus and Lite2 shares common
> nodes like axp805, uart, mmc0 etc and the common differences
> between them is Ethernet is available in One Plus where
> as Wifi, USB3, CSI port is available in Lite2.

You can claim this for pretty much all Allwinner boards, because they mostly
derive from the reference designs Allwinner's design houses put out. Yet we
don't do this for all of them. We do this for boards that are clearly derived
or extended from one another. One example would be the Orange Pi PC and PC Plus.

Do you have any evidence to suggest so? This is not about common device nodes,
but a common hardware design.

ChenYu

> So, add common orangepi nodes into sun50i-h6-orangepi.dtsi
>
> Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>

Re: [PATCH 2/7] arm64: allwinner: h6: Add common orangepi nodes into dtsi

[Jagan Teki]

On Thu, Nov 1, 2018 at 8:23 AM Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> wrote:
>
> On Thu, Nov 1, 2018 at 2:37 AM Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> wrote:
> >
> > Orangepi H6 boards, One Plus and Lite2 shares common
> > nodes like axp805, uart, mmc0 etc and the common differences
> > between them is Ethernet is available in One Plus where
> > as Wifi, USB3, CSI port is available in Lite2.
>
> You can claim this for pretty much all Allwinner boards, because they mostly
> derive from the reference designs Allwinner's design houses put out. Yet we
> don't do this for all of them. We do this for boards that are clearly derived
> or extended from one another. One example would be the Orange Pi PC and PC Plus.
>
> Do you have any evidence to suggest so? This is not about common device nodes,
> but a common hardware design.

I got this information from hardware schematics and from Steven (added
in to list), he too claimed the same.

Re: [PATCH 2/7] arm64: allwinner: h6: Add common orangepi nodes into dtsi

[Chen-Yu Tsai]

On Thu, Nov 1, 2018 at 3:13 PM Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> wrote:
>
> On Thu, Nov 1, 2018 at 8:23 AM Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> wrote:
> >
> > On Thu, Nov 1, 2018 at 2:37 AM Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> wrote:
> > >
> > > Orangepi H6 boards, One Plus and Lite2 shares common
> > > nodes like axp805, uart, mmc0 etc and the common differences
> > > between them is Ethernet is available in One Plus where
> > > as Wifi, USB3, CSI port is available in Lite2.
> >
> > You can claim this for pretty much all Allwinner boards, because they mostly
> > derive from the reference designs Allwinner's design houses put out. Yet we
> > don't do this for all of them. We do this for boards that are clearly derived
> > or extended from one another. One example would be the Orange Pi PC and PC Plus.
> >
> > Do you have any evidence to suggest so? This is not about common device nodes,
> > but a common hardware design.
>
> I got this information from hardware schematics and from Steven (added
> in to list), he too claimed the same.

Good. Please add that to the commit message. The vendor's intentions are as
important as the actual facts.

ChenYu

[PATCH 3/7] arm64: allwinner: h6: Add OrangePi Lite2 initial support

[Jagan Teki]

From: Jagan Teki <jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>

OrangePi Lite2 is Allwinner H6 based open-source SBC,
which support:
- Allwinner H6 Quad-core 64-bit ARM Cortex-A53
- GPU Mali-T720
- 1GB LPDDR3 RAM
- AXP805 PMIC
- AP6356S Wifi/BT
- USB 2.0, USB 3.0 Host, OTG
- HDMI port
- 5V/2A DC power supply

Signed-off-by: Jagan Teki <jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
---
 arch/arm64/boot/dts/allwinner/Makefile                |  1 +
 .../boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts   | 11 +++++++++++
 2 files changed, 12 insertions(+)
 create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts

diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
index 8d4f97f279e0..38f4a015637c 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -18,5 +18,6 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts
new file mode 100644
index 000000000000..e098a2475f2d
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
+ */
+
+#include "sun50i-h6-orangepi.dtsi"
+
+/ {
+	model = "OrangePi Lite2";
+	compatible = "xunlong,orangepi-lite2", "allwinner,sun50i-h6";
+};
-- 
2.18.0.321.gffc6fa0e3

[PATCH 4/7] arm64: allwinner: h6: Add MMC1 pinmux

[Jagan Teki]

MMC1 controlled is already added, but mmc1 pinmux would
need to function SDIO.

So, add support for it.

Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 040828d2e2c0..3b9da12e65db 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -157,6 +157,14 @@
 				bias-pull-up;
 			};
 
+			mmc1_pins: mmc1-pins {
+				pins = "PG0", "PG1", "PG2", "PG3",
+				       "PG4", "PG5";
+				function = "mmc1";
+				drive-strength = <30>;
+				bias-pull-up;
+			};
+
 			mmc2_pins: mmc2-pins {
 				pins = "PC1", "PC4", "PC5", "PC6",
 				       "PC7", "PC8", "PC9", "PC10",
-- 
2.18.0.321.gffc6fa0e3

[PATCH 6/7] arm64: allwinner: h6: Add RTC clock to phandle 32kHz external oscillator

[Jagan Teki]

From: Jagan Teki <jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>

Outside of SOC few chips need external clock source through RTC example
Wifi chip. So H6 RTC clock node need to phandle 32kHz external oscillator
like A64 RTC.

Add support for it.

prefix rtc- with clock-output-names defined in dt-binding to avoid
confusion with existing osc32k name.

Signed-off-by: Jagan Teki <jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
---
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index c8d2fe76da7e..028ec286aa0a 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -271,6 +271,9 @@
 			reg = <0x7000000 0x400>;
 			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+			clock-output-names = "rtc-osc32k", "rtc-osc32k-out";
+			clocks = <&osc32k>;
+			#clock-cells = <1>;
 		};
 
 		r_ccu: clock@7010000 {
-- 
2.18.0.321.gffc6fa0e3

Re: [PATCH 6/7] arm64: allwinner: h6: Add RTC clock to phandle 32kHz external oscillator

[Chen-Yu Tsai]

On Thu, Nov 1, 2018 at 2:37 AM Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> wrote:
>
> From: Jagan Teki <jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
>
> Outside of SOC few chips need external clock source through RTC example
> Wifi chip. So H6 RTC clock node need to phandle 32kHz external oscillator
> like A64 RTC.
>
> Add support for it.

This should be part of the previous patch.

> prefix rtc- with clock-output-names defined in dt-binding to avoid
> confusion with existing osc32k name.

Unfortunately we have a not so documented requirement that the actual
LOSC be named "osc32k", which is why you see all the previous dtsi files
with RTC clock outputs having the external 32k crystal named "ext-osc32k".

ChenYu

> Signed-off-by: Jagan Teki <jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
> ---
>  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> index c8d2fe76da7e..028ec286aa0a 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> @@ -271,6 +271,9 @@
>                         reg = <0x7000000 0x400>;
>                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
>                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
> +                       clock-output-names = "rtc-osc32k", "rtc-osc32k-out";
> +                       clocks = <&osc32k>;
> +                       #clock-cells = <1>;
>                 };
>
>                 r_ccu: clock@7010000 {
> --
> 2.18.0.321.gffc6fa0e3
>

[PATCH 5/7] arm64: allwinner: h6: Add RTC node

[Jagan Teki]

From: Jagan Teki <jagan@openedev.com>

RTC controller is similar to A31, so use the same compatible
for H6 and update interrupt numbers as per manual.

Signed-off-by: Jagan Teki <jagan@openedev.com>
---
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 3b9da12e65db..c8d2fe76da7e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -266,6 +266,13 @@
 			status = "disabled";
 		};
 
+		rtc: rtc@7000000 {
+			compatible = "allwinner,sun6i-a31-rtc";
+			reg = <0x7000000 0x400>;
+			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		r_ccu: clock@7010000 {
 			compatible = "allwinner,sun50i-h6-r-ccu";
 			reg = <0x07010000 0x400>;
-- 
2.18.0.321.gffc6fa0e3

Re: [PATCH 5/7] arm64: allwinner: h6: Add RTC node

[Chen-Yu Tsai]

On Thu, Nov 1, 2018 at 2:37 AM Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> wrote:
>
> From: Jagan Teki <jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
>
> RTC controller is similar to A31, so use the same compatible
> for H6 and update interrupt numbers as per manual.

No. Unfortunately they are not that compatible. The A31 does not have
the RTC clock output. So everyone got it wrong. :( Plus the clock rate
of the internal RC oscillator varies between SoCs. I'm working on a
series of patches to correct this. Stay tuned.

ChenYu

Re: [PATCH 5/7] arm64: allwinner: h6: Add RTC node

[Jagan Teki]

On Thu, Nov 1, 2018 at 8:25 AM Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> wrote:
>
> On Thu, Nov 1, 2018 at 2:37 AM Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> wrote:
> >
> > From: Jagan Teki <jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
> >
> > RTC controller is similar to A31, so use the same compatible
> > for H6 and update interrupt numbers as per manual.
>
> No. Unfortunately they are not that compatible. The A31 does not have
> the RTC clock output. So everyone got it wrong. :( Plus the clock rate
> of the internal RC oscillator varies between SoCs. I'm working on a
> series of patches to correct this. Stay tuned.

4 bit, EXT_LOSC_EN of LOSC_CTRL_REG (0x00) seem available in H6. I can
see external clock working with WIFI for A31 compatible.

Re: [PATCH 5/7] arm64: allwinner: h6: Add RTC node

[Chen-Yu Tsai]

On Thu, Nov 1, 2018 at 3:33 PM Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> wrote:
>
> On Thu, Nov 1, 2018 at 8:25 AM Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> wrote:
> >
> > On Thu, Nov 1, 2018 at 2:37 AM Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> wrote:
> > >
> > > From: Jagan Teki <jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
> > >
> > > RTC controller is similar to A31, so use the same compatible
> > > for H6 and update interrupt numbers as per manual.
> >
> > No. Unfortunately they are not that compatible. The A31 does not have
> > the RTC clock output. So everyone got it wrong. :( Plus the clock rate
> > of the internal RC oscillator varies between SoCs. I'm working on a
> > series of patches to correct this. Stay tuned.
>
> 4 bit, EXT_LOSC_EN of LOSC_CTRL_REG (0x00) seem available in H6. I can
> see external clock working with WIFI for A31 compatible.

That bit turns on the external crystal, i.e. X32KIN and X32KOUT pins.

I'm talking about the X32KFOUT pin, which feeds the WiFi module the
LPO clock in typical Allwinner designs. That is controlled by register
0x60, and is not present on the A31. That is the clock you say is
working. You have the two confused.

The clock tree looks like this:

IOSC -----------------------------\
                                   SUN6I_LOSC_CTRL_EXT_OSC mux ---->
LOSC --> (to CCU)
32k crystal --> EXT_LOSC_EN gate -/                              \
                                                                  \
                                                                  /
      (to WiFi) <-- X32KFOUT pin <-- LOSC_OUT_GATING_EN gate <---/

The bottom part does not exist in the A31. Meanwhile we've been claiming that
all later RTC modules that actually have that part are compatible with the A31.
Also the IOSC part has different clock rates for different chips.

Do you see the problem?


ChenYu

Re: [PATCH 5/7] arm64: allwinner: h6: Add RTC node

[Jagan Teki]

On Thu, Nov 1, 2018 at 1:23 PM Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> wrote:
>
> On Thu, Nov 1, 2018 at 3:33 PM Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> wrote:
> >
> > On Thu, Nov 1, 2018 at 8:25 AM Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> wrote:
> > >
> > > On Thu, Nov 1, 2018 at 2:37 AM Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> wrote:
> > > >
> > > > From: Jagan Teki <jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
> > > >
> > > > RTC controller is similar to A31, so use the same compatible
> > > > for H6 and update interrupt numbers as per manual.
> > >
> > > No. Unfortunately they are not that compatible. The A31 does not have
> > > the RTC clock output. So everyone got it wrong. :( Plus the clock rate
> > > of the internal RC oscillator varies between SoCs. I'm working on a
> > > series of patches to correct this. Stay tuned.
> >
> > 4 bit, EXT_LOSC_EN of LOSC_CTRL_REG (0x00) seem available in H6. I can
> > see external clock working with WIFI for A31 compatible.
>
> That bit turns on the external crystal, i.e. X32KIN and X32KOUT pins.

This is what I confused, the same signal pins available there in A64
schematics but no bit to enable external OSC in LOSC_CTRL_REG.

But the X32KFOUT pin which is 0x60 , BIT(0) is enabled in A64, H6 w/o
this LOSC_CTRL_REG which I don't know exactly or may be feed it by
default not sure.

>
> I'm talking about the X32KFOUT pin, which feeds the WiFi module the
> LPO clock in typical Allwinner designs. That is controlled by register
> 0x60, and is not present on the A31. That is the clock you say is
> working. You have the two confused.
>
> The clock tree looks like this:
>
> IOSC -----------------------------\
>                                    SUN6I_LOSC_CTRL_EXT_OSC mux ---->
> LOSC --> (to CCU)
> 32k crystal --> EXT_LOSC_EN gate -/                              \
>                                                                   \
>                                                                   /
>       (to WiFi) <-- X32KFOUT pin <-- LOSC_OUT_GATING_EN gate <---/

Yes, I understand this. But for A33, A64 there is no EXT_LOSC_EN which
is directly feed to WIFI from LOSC as per manual but from schematic
signals X32KI and X32KO were present.

>
> The bottom part does not exist in the A31. Meanwhile we've been claiming that
> all later RTC modules that actually have that part are compatible with the A31.
> Also the IOSC part has different clock rates for different chips.
>
> Do you see the problem?

>From external crystal point of view, between A33, A64 vs H6 I only see
the difference in EXT_LOSC_EN external oscillator enable bit only
available in H6 manual.

Regarding, rtc-sun6i. we can manage the external clock stuff via
"clock-output-names" with rtc->ext_losc and mentioning external
oscillator outputs on DTSI. since A31, don't have external clock to
wifi then we can skip those properties.

What do you think?

Re: [PATCH 5/7] arm64: allwinner: h6: Add RTC node

[Chen-Yu Tsai]

On Thu, Nov 1, 2018 at 5:02 PM Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> wrote:
>
> On Thu, Nov 1, 2018 at 1:23 PM Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> wrote:
> >
> > On Thu, Nov 1, 2018 at 3:33 PM Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> wrote:
> > >
> > > On Thu, Nov 1, 2018 at 8:25 AM Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> wrote:
> > > >
> > > > On Thu, Nov 1, 2018 at 2:37 AM Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> wrote:
> > > > >
> > > > > From: Jagan Teki <jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
> > > > >
> > > > > RTC controller is similar to A31, so use the same compatible
> > > > > for H6 and update interrupt numbers as per manual.
> > > >
> > > > No. Unfortunately they are not that compatible. The A31 does not have
> > > > the RTC clock output. So everyone got it wrong. :( Plus the clock rate
> > > > of the internal RC oscillator varies between SoCs. I'm working on a
> > > > series of patches to correct this. Stay tuned.
> > >
> > > 4 bit, EXT_LOSC_EN of LOSC_CTRL_REG (0x00) seem available in H6. I can
> > > see external clock working with WIFI for A31 compatible.
> >
> > That bit turns on the external crystal, i.e. X32KIN and X32KOUT pins.
>
> This is what I confused, the same signal pins available there in A64
> schematics but no bit to enable external OSC in LOSC_CTRL_REG.
>
> But the X32KFOUT pin which is 0x60 , BIT(0) is enabled in A64, H6 w/o
> this LOSC_CTRL_REG which I don't know exactly or may be feed it by
> default not sure.
>
> >
> > I'm talking about the X32KFOUT pin, which feeds the WiFi module the
> > LPO clock in typical Allwinner designs. That is controlled by register
> > 0x60, and is not present on the A31. That is the clock you say is
> > working. You have the two confused.
> >
> > The clock tree looks like this:
> >
> > IOSC -----------------------------\
> >                                    SUN6I_LOSC_CTRL_EXT_OSC mux ---->
> > LOSC --> (to CCU)
> > 32k crystal --> EXT_LOSC_EN gate -/                              \
> >                                                                   \
> >                                                                   /
> >       (to WiFi) <-- X32KFOUT pin <-- LOSC_OUT_GATING_EN gate <---/
>
> Yes, I understand this. But for A33, A64 there is no EXT_LOSC_EN which
> is directly feed to WIFI from LOSC as per manual but from schematic
> signals X32KI and X32KO were present.

No. Read the schematic again. CAREFULLY. The pin that feeds the WiFi module
is called X32KFOUT. With an "F". The A33 datasheet says the pin is "Clock
Output of LOSC (X32KFOUT can be gating)". The A64 datasheet may not mention
the output can be gated, but the LOSC_OUT_GATING_REG register is aptly named
"LOSC Output Gating Register".

And see below about the EXT_LOSC_EN bit. You are confusing input to the RTC
module vs output from the RTC module. All crystals have an IN and an OUT
connection. It's just the way they work.

> > The bottom part does not exist in the A31. Meanwhile we've been claiming that
> > all later RTC modules that actually have that part are compatible with the A31.
> > Also the IOSC part has different clock rates for different chips.
> >
> > Do you see the problem?
>
> From external crystal point of view, between A33, A64 vs H6 I only see
> the difference in EXT_LOSC_EN external oscillator enable bit only
> available in H6 manual.

You are focusing on the wrong thing. From the driver's point of view,
we simply don't care about this bit. It is by default on. We might want
to force enable it if some broken bootloader turns it off, but that is
besides the point here. And on all the other SoCs, the absence of this
bit means that the external crystal will always be on.

Furthermore, this bit concerns the "input" from the crystal to the RTC.
What I'm concerned about, and what you should be concerned about, because
that's what you're using, is the LOSC_OUT_GATING_EN bit. As mentioned this
does not exist on the A31.

>
> Regarding, rtc-sun6i. we can manage the external clock stuff via
> "clock-output-names" with rtc->ext_losc and mentioning external
> oscillator outputs on DTSI. since A31, don't have external clock to
> wifi then we can skip those properties.
>
> What do you think?

That's not correct. On the A31, the RTC's LOSC still feeds the CCU,
so output index 0 is always valid. Output index 1 on the A31 is invalid
because it simply doesn't have this in the hardware. Furthermore, you're
still not dealing with the fact that one A23/A33 the IOSC is 600~700 kHZ,
on the A64/H3/H5/H6 it is 16 MHz, and on the V3/V3s it is 32 kHz. The
first two cases also have prescalers to divide the clock rate down to
around 32 kHz. All these hardware details need to be tied to new compatible
strings, so that the driver knows about them and can handle them if needed.
What you're describing is very fragile and pretty much a hack. We already
have enough of those.

ChenYu

[RFC PATCH 7/7] arm64: allwinner: h6: orangepi-liet2: Enable AP6356S WiFi support

[Jagan Teki]

From: Jagan Teki <jagan@openedev.com>

Enable AP6356S WiFi/BT combo chip on Orangepi Lite2 board:
- WiFi SDIO interface is connected to MMC1
- WiFi WL-PMU-EN pin connected to gpio PM3: attach to mmc-pwrseq
- WiFi WL-WAKE-AP pin connected to gpio PM0
- 32kHz external oscillator gate clock from RTC

Signed-off-by: Jagan Teki <jagan@openedev.com>
---
Note:
- chip detected, but failed to connect
[  129.084504] brcmfmac: brcmf_sdio_hostmail: mailbox indicates firmware halted
[  135.906409] brcmfmac: brcmf_sdio_bus_rxctl: resumed on timeout 

 .../allwinner/sun50i-h6-orangepi-lite2.dts    | 27 +++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts
index e098a2475f2d..b8012208c185 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts
@@ -8,4 +8,31 @@
 / {
 	model = "OrangePi Lite2";
 	compatible = "xunlong,orangepi-lite2", "allwinner,sun50i-h6";
+
+	wifi_pwrseq: wifi-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rtc 1>;
+		clock-names = "ext_clock";
+		reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* WL-REG-ON: PM3 */
+		post-power-on-delay-ms = <200>;
+	};
+};
+
+&mmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins>;
+	vmmc-supply = <&reg_cldo2>;
+	vqmmc-supply = <&reg_bldo3>;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+
+	brcmf: wifi@1 {
+		reg = <1>;
+		compatible = "brcm,bcm4329-fmac";
+		interrupt-parent = <&r_pio>;
+		interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>;	/* WL-WAKE-AP: PM0 */
+		interrupt-names = "host-wake";
+	};
 };
-- 
2.18.0.321.gffc6fa0e3

Re: [RFC PATCH 7/7] arm64: allwinner: h6: orangepi-liet2: Enable AP6356S WiFi support

[Jagan Teki]

On Thu, Nov 1, 2018 at 12:07 AM Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> wrote:
>
> From: Jagan Teki <jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
>
> Enable AP6356S WiFi/BT combo chip on Orangepi Lite2 board:
> - WiFi SDIO interface is connected to MMC1
> - WiFi WL-PMU-EN pin connected to gpio PM3: attach to mmc-pwrseq
> - WiFi WL-WAKE-AP pin connected to gpio PM0
> - 32kHz external oscillator gate clock from RTC
>
> Signed-off-by: Jagan Teki <jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
> ---
> Note:
> - chip detected, but failed to connect
> [  129.084504] brcmfmac: brcmf_sdio_hostmail: mailbox indicates firmware halted
> [  135.906409] brcmfmac: brcmf_sdio_bus_rxctl: resumed on timeout

This got fixed. Will send next version.

Re: [RFC PATCH 7/7] arm64: allwinner: h6: orangepi-liet2: Enable AP6356S WiFi support

[Chen-Yu Tsai]

On Thu, Nov 1, 2018 at 3:35 PM Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> wrote:
>
> On Thu, Nov 1, 2018 at 12:07 AM Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> wrote:
> >
> > From: Jagan Teki <jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
> >
> > Enable AP6356S WiFi/BT combo chip on Orangepi Lite2 board:
> > - WiFi SDIO interface is connected to MMC1
> > - WiFi WL-PMU-EN pin connected to gpio PM3: attach to mmc-pwrseq
> > - WiFi WL-WAKE-AP pin connected to gpio PM0
> > - 32kHz external oscillator gate clock from RTC

You never specified a clock rate for it, so it might actually be wrong.
The default clock rate would be something "around" 32 kHz, but not very
accurate. Meanwhile the WiFi module would have very specific requirements
on frequency and accuracy of this clock. The WiFi part doesn't seem to
care that much, but the Bluetooth part cares very much. It doesn't work
or it would seem to work but you don't get anything off the radio if the
frequency is off (as in off-frequency).

> >
> > Signed-off-by: Jagan Teki <jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
> > ---
> > Note:
> > - chip detected, but failed to connect
> > [  129.084504] brcmfmac: brcmf_sdio_hostmail: mailbox indicates firmware halted
> > [  135.906409] brcmfmac: brcmf_sdio_bus_rxctl: resumed on timeout
>
> This got fixed. Will send next version.

Could you wait until I get my RTC changes out? I also have some Bluetooth
patches for AP621x, which is what started all this RTC work, which you might
find interesting.

ChenYu

Re: [RFC PATCH 7/7] arm64: allwinner: h6: orangepi-liet2: Enable AP6356S WiFi support

[Jagan Teki]

On Thu, Nov 1, 2018 at 1:28 PM Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> wrote:
>
> On Thu, Nov 1, 2018 at 3:35 PM Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> wrote:
> >
> > On Thu, Nov 1, 2018 at 12:07 AM Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> wrote:
> > >
> > > From: Jagan Teki <jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
> > >
> > > Enable AP6356S WiFi/BT combo chip on Orangepi Lite2 board:
> > > - WiFi SDIO interface is connected to MMC1
> > > - WiFi WL-PMU-EN pin connected to gpio PM3: attach to mmc-pwrseq
> > > - WiFi WL-WAKE-AP pin connected to gpio PM0
> > > - 32kHz external oscillator gate clock from RTC
>
> You never specified a clock rate for it, so it might actually be wrong.
> The default clock rate would be something "around" 32 kHz, but not very
> accurate. Meanwhile the WiFi module would have very specific requirements
> on frequency and accuracy of this clock. The WiFi part doesn't seem to
> care that much, but the Bluetooth part cares very much. It doesn't work
> or it would seem to work but you don't get anything off the radio if the
> frequency is off (as in off-frequency).

True, but why it's not 32K which is stated in manual and schematics do
we need to measure the actual rate with oscilloscope?

>
> > >
> > > Signed-off-by: Jagan Teki <jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
> > > ---
> > > Note:
> > > - chip detected, but failed to connect
> > > [  129.084504] brcmfmac: brcmf_sdio_hostmail: mailbox indicates firmware halted
> > > [  135.906409] brcmfmac: brcmf_sdio_bus_rxctl: resumed on timeout
> >
> > This got fixed. Will send next version.
>
> Could you wait until I get my RTC changes out? I also have some Bluetooth
> patches for AP621x, which is what started all this RTC work, which you might
> find interesting.

Yes, my intention is the same.

Re: [RFC PATCH 7/7] arm64: allwinner: h6: orangepi-liet2: Enable AP6356S WiFi support

[Chen-Yu Tsai]

On Thu, Nov 1, 2018 at 5:08 PM Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> wrote:
>
> On Thu, Nov 1, 2018 at 1:28 PM Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> wrote:
> >
> > On Thu, Nov 1, 2018 at 3:35 PM Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> wrote:
> > >
> > > On Thu, Nov 1, 2018 at 12:07 AM Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> wrote:
> > > >
> > > > From: Jagan Teki <jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
> > > >
> > > > Enable AP6356S WiFi/BT combo chip on Orangepi Lite2 board:
> > > > - WiFi SDIO interface is connected to MMC1
> > > > - WiFi WL-PMU-EN pin connected to gpio PM3: attach to mmc-pwrseq
> > > > - WiFi WL-WAKE-AP pin connected to gpio PM0
> > > > - 32kHz external oscillator gate clock from RTC
> >
> > You never specified a clock rate for it, so it might actually be wrong.
> > The default clock rate would be something "around" 32 kHz, but not very
> > accurate. Meanwhile the WiFi module would have very specific requirements
> > on frequency and accuracy of this clock. The WiFi part doesn't seem to
> > care that much, but the Bluetooth part cares very much. It doesn't work
> > or it would seem to work but you don't get anything off the radio if the
> > frequency is off (as in off-frequency).
>
> True, but why it's not 32K which is stated in manual and schematics do
> we need to measure the actual rate with oscilloscope?

I suppose it's just shorthand. The datasheet describes the actual requirements
for both oscillators, where it clearly states the 32K one should be 32768 Hz.
A scope shouldn't be needed as we expect the board design to at least conform
to constraints outlined in datasheets.

On the side, the LOSC be _around_ 32kHz if you clocked it from the internal
RC oscillator, which is not very stable. This is actually the hardware default.
But the WiFi module (and also the RTC) needs 32.768K, a slight difference,
but enough to throw off calculations for other clocks. When the RTC module
isn't clocked from the external crystal, the RTC clock will drift. This has
been reported and is why we have

    /* Switch to the external, more precise, oscillator */
    writel(SUN6I_LOSC_CTRL_KEY | SUN6I_LOSC_CTRL_EXT_OSC,
           rtc->base + SUN6I_LOSC_CTRL);

in the RTC driver's clock probe function. See these two patches:

    fb61bb82cb46 rtc: sun6i: Switch to the external oscillator
    3855c2c3e546 rtc: sun6i: Expose the 32kHz oscillator

Note the commit message for the second patch is incorrect. We actually force
the RTC module to use the external crystal regardless of the "clocks" property.

I actually forgot about this. So even without assigning clock rates your patch
would work fine. Hope this doesn't confuse you more than it already has.

ChenYu

> > > > Signed-off-by: Jagan Teki <jagan-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
> > > > ---
> > > > Note:
> > > > - chip detected, but failed to connect
> > > > [  129.084504] brcmfmac: brcmf_sdio_hostmail: mailbox indicates firmware halted
> > > > [  135.906409] brcmfmac: brcmf_sdio_bus_rxctl: resumed on timeout
> > >
> > > This got fixed. Will send next version.
> >
> > Could you wait until I get my RTC changes out? I also have some Bluetooth
> > patches for AP621x, which is what started all this RTC work, which you might
> > find interesting.
>
> Yes, my intention is the same.

Re: [PATCH 1/7] clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width

[Maxime Ripard]

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On Thu, Nov 01, 2018 at 12:06:28AM +0530, Jagan Teki wrote:
> MUX bits for MMC clock register range are 25:24 where 24 is shift
> and 2 is width So fix the width number from 3 to 2.
> 
> Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

Applied for 4.21, thanks!
Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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