From: Matthias Kaehlcke <mka-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
To: Doug Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Archit Taneja <architt-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
ryadav-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
David Airlie <airlied-cv59FeDIM0c@public.gmane.org>,
linux-arm-msm
<linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
LKML <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
dri-devel
<dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>,
Stephen Boyd <swboyd-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
Rob Clark <robdclark-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
freedreno
<freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Subject: Re: [PATCH 2/2] drm/msm/dsi: Get PHY ref clock from the DT
Date: Wed, 14 Nov 2018 15:56:30 -0800 [thread overview]
Message-ID: <20181114235630.GO22824@google.com> (raw)
In-Reply-To: <CAD=FV=Vyv5sRhJNgpP6Gnn3+6zRjGsT8RozCY6xx51Tr_hRoeg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Thu, Nov 08, 2018 at 02:04:31PM -0800, Doug Anderson wrote:
> Hi,
>
> On Fri, Nov 2, 2018 at 2:45 PM Matthias Kaehlcke <mka@chromium.org> wrote:
> >
> > Get the PHY ref clock from the device tree instead of hardcoding
> > its name and rate.
> >
> > Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
> > ---
> > drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 11 ++++++++++-
> > 1 file changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> > index 4c03f0b7343ed..1016eb50df8f5 100644
> > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> > +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> > @@ -91,6 +91,8 @@ struct dsi_pll_10nm {
> > void __iomem *phy_cmn_mmio;
> > void __iomem *mmio;
> >
> > + struct clk *vco_ref_clk;
> > +
> > u64 vco_ref_clk_rate;
> > u64 vco_current_rate;
> >
> > @@ -630,7 +632,8 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)
> > char clk_name[32], parent[32], vco_name[32];
> > char parent2[32], parent3[32], parent4[32];
> > struct clk_init_data vco_init = {
> > - .parent_names = (const char *[]){ "xo" },
> > + .parent_names = (const char *[]){
> > + __clk_get_name(pll_10nm->vco_ref_clk) },
> > .num_parents = 1,
> > .name = vco_name,
> > .flags = CLK_IGNORE_UNUSED,
> > @@ -786,6 +789,12 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id)
> > pll_10nm->id = id;
> > pll_10nm_list[id] = pll_10nm;
> >
> > + pll_10nm->vco_ref_clk = devm_clk_get(&pdev->dev, "ref");
> > + if (IS_ERR(pll_10nm->vco_ref_clk)) {
> > + dev_err(&pdev->dev, "couldn't get 'ref' clock\n");
> > + return (void *)pll_10nm->vco_ref_clk;
> > + }
>
> So, ummmm. Can you follow the same pattern for all the other clocks
> in this file too? All parents should get their name based on
> references in the device tree.
>
> It turns out that right now we have a mismatch because
> "drivers/clk/qcom/dispcc-sdm845.c" calls "dsi0pllbyte"
> "dsi0_phy_pll_out_byteclk" and calls "dsi0pll"
> "dsi0_phy_pll_out_dsiclk". We might want to change the names in
> dispcc-sdm845.c, but it wouldn't matter if we simply didn't hardcode
> them here.
Hm, I understand the problem, but not quite what you mean with 'follow
the same pattern'. The VCO ref clock is an 'external'/existing clock,
hence it can be specificed in the DT and obtained with
_clk_get(). However the clocks you mention above are 'created' by the
PHY driver, so we could only specify their names in the DT, not sure
if that's what you are suggesting. I guess 'clock-output-names' could
be used, though it isn't really useful to describe the names in a
clock tree. If you still think this should be done please share how
you envision the DT entries to look.
Cheers
Matthias
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next prev parent reply other threads:[~2018-11-14 23:56 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-02 21:45 [PATCH 1/2] dt-bindings: msm/dsi: Add ref clock for 10nm PHY Matthias Kaehlcke
[not found] ` <20181102214534.184593-1-mka-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-11-02 21:45 ` [PATCH 2/2] drm/msm/dsi: Get PHY ref clock from the DT Matthias Kaehlcke
2018-11-05 17:33 ` [Freedreno] " Sean Paul
2018-11-14 21:08 ` Matthias Kaehlcke
2018-11-06 23:11 ` Stephen Boyd
2018-11-14 22:24 ` Matthias Kaehlcke
[not found] ` <20181114222443.GL22824-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
2018-11-14 23:30 ` Stephen Boyd
[not found] ` <20181102214534.184593-2-mka-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-11-08 22:04 ` Doug Anderson
[not found] ` <CAD=FV=Vyv5sRhJNgpP6Gnn3+6zRjGsT8RozCY6xx51Tr_hRoeg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-11-14 23:56 ` Matthias Kaehlcke [this message]
2018-11-20 22:41 ` Doug Anderson
2018-11-05 17:34 ` [PATCH 1/2] dt-bindings: msm/dsi: Add ref clock for 10nm PHY Sean Paul
2018-11-06 23:09 ` Stephen Boyd
[not found] ` <154154578082.88331.1035410665298962611-n1Xw8LXHxjTHt/MElyovVYaSKrA+ACpX0E9HWUfgJXw@public.gmane.org>
2018-11-14 22:42 ` Matthias Kaehlcke
[not found] ` <20181114224252.GM22824-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
2018-11-14 23:32 ` Stephen Boyd
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