From mboxrd@z Thu Jan  1 00:00:00 1970
From: David Miller <davem@davemloft.net>
Subject: Re: [PATCH v2 0/7] IP101GR: devicetree based configuration of
 SEL_INTR32
Date: Sun, 18 Nov 2018 16:16:40 -0800 (PST)
Message-ID: <20181118.161640.141528330634887893.davem@davemloft.net>
References: <20181118212359.32414-1-martin.blumenstingl@googlemail.com>
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From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Date: Sun, 18 Nov 2018 22:23:52 +0100

> The IP101GR is a 32-pin QFN package variant of the IP101G/IP101GA
> Ethernet PHY. Due to it's limited amount of pins the RXER (receive
> error) and INTR32 (interrupt) functions share pin 21.
 ...

Series applied to net-next, thank you.