From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH v4 03/26] clk: sunxi-ng: Add check for maximum rate to NKM PLLs Date: Tue, 20 Nov 2018 11:55:57 +0100 Message-ID: <20181120105557.3mysirc3ga2h2334@flea> References: <20181113111633.20189-1-jagan@amarulasolutions.com> <20181113111633.20189-4-jagan@amarulasolutions.com> <20181113132658.niwy6bqdqzaeqpv2@flea> Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="a27mgq4savd3egd2" Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Jagan Teki Cc: Chen-Yu Tsai , Icenowy Zheng , Jernej Skrabec , Vasily Khoruzhick , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , David Airlie , dri-devel , Michael Turquette , Stephen Boyd , linux-clk , Michael Trimarchi , linux-arm-kernel , devicetree , linux-kernel , linux-sunxi@googlegroups.com, linux-amarula@amarulasolutions.com List-Id: devicetree@vger.kernel.org --a27mgq4savd3egd2 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Nov 15, 2018 at 08:51:04PM +0530, Jagan Teki wrote: > > > drivers/clk/sunxi-ng/ccu_nkm.c | 3 +++ > > > drivers/clk/sunxi-ng/ccu_nkm.h | 1 + > > > 2 files changed, 4 insertions(+) > > > > > > diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/cc= u_nkm.c > > > index 6b5ad990f802..b8b66cdd30bf 100644 > > > --- a/drivers/clk/sunxi-ng/ccu_nkm.c > > > +++ b/drivers/clk/sunxi-ng/ccu_nkm.c > > > @@ -128,6 +128,9 @@ static unsigned long ccu_nkm_round_rate(struct cc= u_mux_internal *mux, > > > if (rate < nkm->min_rate) > > > return nkm->min_rate; > > > > > > + if (nkm->max_rate && rate > nkm->max_rate) > > > + return nkm->max_rate; > > > + > > > > I would expect the test to be the same for the minimum and maximum case= s. >=20 > I don't have proper use-case for max rate test, I do verify by using > higher the rate on dclock, but nor sure. May be I can skip the > max_rate patch? So you're sending more patches that you haven't really tested? Why are you sending them then? > Apart from this, any idea about this issue where SUN4I_TCON0_DCLK_REG > will only work with div upto 6 on A64 DSI panels[1], did you find the > same issue on A33? IIRC my panel was falling into the case where the divider was 4, so I've not fallen into that case. > With parent rate 330MHz, the resulting tcon divider for 30MHz [2] > clock is 11 and for the same for 55MHz [3] clock is 6. I'm not sure what the question is? Maxime --=20 Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com --a27mgq4savd3egd2 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCW/PoPQAKCRDj7w1vZxhR xSLGAP9Qr44NyVb197rOJlOKTTntni3+46QV9pevbQM76nN3TgEAgaYjL5W+4KIG hTGncT/uJU90x586s+G6e7AB/3s8/A4= =07n9 -----END PGP SIGNATURE----- --a27mgq4savd3egd2--