From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Packham Subject: [PATCH v7 5/9] dt-bindings: ARM: document marvell,ecc-enable binding Date: Thu, 22 Nov 2018 13:11:38 +1300 Message-ID: <20181122001142.19187-6-chris.packham@alliedtelesis.co.nz> References: <20181122001142.19187-1-chris.packham@alliedtelesis.co.nz> Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <20181122001142.19187-1-chris.packham@alliedtelesis.co.nz> Sender: linux-kernel-owner@vger.kernel.org To: linux@armlinux.org.uk, bp@alien8.de, arnd@arndb.de, jlu@pengutronix.de, gregory.clement@bootlin.com, linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham , Rob Herring , Mark Rutland List-Id: devicetree@vger.kernel.org Add documentation for the marvell,ecc-enable properties which can be used to enable ECC on the Marvell aurora cache. Signed-off-by: Chris Packham Reviewed-by: Rob Herring --- Notes: =20 Changes in v7: =20 - remove marvell,ecc-disable =20 Changes in v6: =20 - new (split binding doc from implementation). =20Documentation/devicetree/bindings/arm/l2c2x0.txt | 1 + =201 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documenta= tion/devicetree/bindings/arm/l2c2x0.txt index fbe6cb21f4cf..69e890d56392 100644 --- a/Documentation/devicetree/bindings/arm/l2c2x0.txt +++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt @@ -76,6 +76,7 @@ Optional properties: =20 specified to indicate that such transforms are precluded. =20- arm,parity-enable : enable parity checking on the L2 cache (L220 or = PL310). =20- arm,parity-disable : disable parity checking on the L2 cache (L220 o= r PL310). +- marvell,ecc-enable : enable ECC protection on the L2 cache =20- arm,outer-sync-disable : disable the outer sync operation on the L2 = cache. =20 Some core tiles, especially ARM PB11MPCore have a faulty L220 cache = that =20 will randomly hang unless outer sync operations are disabled. --=20 2.19.1