From: Anand Moon <linux.amoon@gmail.com>
To: Kukjin Kim <kgene@kernel.org>,
linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>,
Tomasz Figa <tomasz.figa@gmail.com>,
Chanwoo Choi <cw00.choi@samsung.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Krzysztof Kozlowski <krzk@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Andrzej Hajda <a.hajda@samsung.com>
Subject: [PATCH 2/3] clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_sclk_vpll
Date: Fri, 23 Nov 2018 09:44:12 +0000 [thread overview]
Message-ID: <20181123094413.1108-2-linux.amoon@gmail.com> (raw)
In-Reply-To: <20181123094413.1108-1-linux.amoon@gmail.com>
This allows changing the VPLL output frequency through the g3d subsystem
clock tree leaf clocks.
Cc: Andrzej Hajda <a.hajda@samsung.com>
Cc: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
drivers/clk/samsung/clk-exynos5420.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 34156bdfd0d2..6bf1b2e89106 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -647,7 +647,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1),
MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
- MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
+ MUX_F(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1,
+ CLK_SET_RATE_PARENT, 0),
MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
--
2.17.1
next prev parent reply other threads:[~2018-11-23 9:44 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20181123094453epcas4p16be0412e0195fe4bf06680111805352a@epcas4p1.samsung.com>
2018-11-23 9:44 ` [PATCH 1/3] clk: samsung: exynos5420: add VPLL rate table for g3d clock Anand Moon
2018-11-23 9:44 ` Anand Moon [this message]
2018-11-23 9:44 ` [PATCH 3/3] ARM: dts: Add g3d bus nodes using VDD_INT for Exynos542x SoC Anand Moon
2018-11-26 7:37 ` Chanwoo Choi
2018-11-26 8:49 ` Anand Moon
2018-11-26 7:48 ` [PATCH 1/3] clk: samsung: exynos5420: add VPLL rate table for g3d clock Chanwoo Choi
2018-11-26 8:51 ` Anand Moon
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