From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-f66.google.com ([209.85.208.66]:35664 "EHLO mail-ed1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727724AbeK1Uzo (ORCPT ); Wed, 28 Nov 2018 15:55:44 -0500 From: Thierry Reding Subject: [PATCH v3 10/12] arm64: tegra: Add nodes for TCU on Tegra194 Date: Wed, 28 Nov 2018 10:54:19 +0100 Message-Id: <20181128095421.20573-11-thierry.reding@gmail.com> In-Reply-To: <20181128095421.20573-1-thierry.reding@gmail.com> References: <20181128095421.20573-1-thierry.reding@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: devicetree-owner@vger.kernel.org To: Thierry Reding , Jassi Brar Cc: Greg Kroah-Hartman , Jiri Slaby , Mikko Perttunen , Jon Hunter , Timo Alho , Pekka Pessi , Mika Liljeberg , linux-tegra@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org List-ID: From: Mikko Perttunen Add nodes required for communication through the Tegra Combined UART. This includes the AON HSP instance, addition of shared interrupts for the TOP0 HSP instance, and finally the TCU node itself. Also mark the HSP instances as compatible to tegra194-hsp, as the hardware is not identical but is compatible to tegra186-hsp. Signed-off-by: Mikko Perttunen Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- Changes in v2: - encode direction of mailboxes in device tree mailbox specifier --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 38 ++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index d64fe306d2e4..1d8ed688fe59 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -688,10 +688,35 @@ }; hsp_top0: hsp@3c00000 { - compatible = "nvidia,tegra186-hsp"; + compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; reg = <0x03c00000 0xa0000>; - interrupts = ; - interrupt-names = "doorbell"; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "doorbell", "shared0", "shared1", "shared2", + "shared3", "shared4", "shared5", "shared6", + "shared7"; + #mbox-cells = <2>; + }; + + hsp_aon: hsp@c150000 { + compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; + reg = <0x0c150000 0xa0000>; + interrupts = , + , + , + ; + /* + * Shared interrupt 0 is routed only to AON/SPE, so + * we only have 4 shared interrupts for the CCPLEX. + */ + interrupt-names = "shared1", "shared2", "shared3", "shared4"; #mbox-cells = <2>; }; @@ -879,6 +904,13 @@ method = "smc"; }; + tcu: tcu { + compatible = "nvidia,tegra194-tcu"; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, + <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; + mbox-names = "rx", "tx"; + }; + thermal-zones { cpu { thermal-sensors = <&{/bpmp/thermal} -- 2.19.1