From: Shawn Guo <shawnguo@kernel.org>
To: Fabio Estevam <festevam@gmail.com>
Cc: devicetree@vger.kernel.org, marc.zyngier@arm.com,
liviu.dudau@arm.com, robh+dt@kernel.org, linux-imx@nxp.com,
kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/2] ARM: dts: imx6ul: Correct mask for GIC PPI interrupts
Date: Wed, 5 Dec 2018 12:14:05 +0800 [thread overview]
Message-ID: <20181205041404.GM3987@dragon> (raw)
In-Reply-To: <1543858820-3354-1-git-send-email-festevam@gmail.com>
On Mon, Dec 03, 2018 at 03:40:19PM -0200, Fabio Estevam wrote:
> The GIC_CPU_MASK_SIMPLE() macro should take as its argument the actual
> number of CPU cores the interrupt controller is wired to.
>
> i.MX6UL contains a single Cortex-A7, hence the second interrupt specifier
> cell for Private Peripheral Interrupts should use "GIC_CPU_MASK_SIMPLE(1)".
>
> Tested on a imx6ul-evk.
>
> Signed-off-by: Fabio Estevam <festevam@gmail.com>
Dropped RFC patches (shouldn't be applied at all, sorry), and applied
these two.
Shawn
prev parent reply other threads:[~2018-12-05 4:14 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-03 17:40 [PATCH 1/2] ARM: dts: imx6ul: Correct mask for GIC PPI interrupts Fabio Estevam
2018-12-03 17:40 ` [PATCH 2/2] ARM: dts: imx7: " Fabio Estevam
2018-12-05 4:14 ` Shawn Guo [this message]
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