From: Boris Brezillon <boris.brezillon@bootlin.com>
To: Vignesh R <vigneshr@ti.com>
Cc: Marek Vasut <marek.vasut@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Brian Norris <computersforpeace@gmail.com>,
Yogesh Gaur <yogeshnarayan.gaur@nxp.com>,
Linux ARM Mailing List <linux-arm-kernel@lists.infradead.org>,
linux-mtd@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/3] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller
Date: Mon, 10 Dec 2018 09:45:13 +0100 [thread overview]
Message-ID: <20181210094513.6282d55e@bbrezillon> (raw)
In-Reply-To: <20181003165603.2579-4-vigneshr@ti.com>
On Wed, 3 Oct 2018 22:26:03 +0530
Vignesh R <vigneshr@ti.com> wrote:
> Cadence OSPI controller IP supports Octal IO (x8 IO lines),
> It also has an integrated PHY. IP register layout is very
> similar to existing QSPI IP except for additional bits to support Octal
> and Octal DDR mode. Therefore, extend current driver to support Octal
> mode.
>
> Signed-off-by: Vignesh R <vigneshr@ti.com>
> ---
> drivers/mtd/spi-nor/cadence-quadspi.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
> index e24db817154e..48b00e75a879 100644
> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
> @@ -101,6 +101,7 @@ struct cqspi_st {
> #define CQSPI_INST_TYPE_SINGLE 0
> #define CQSPI_INST_TYPE_DUAL 1
> #define CQSPI_INST_TYPE_QUAD 2
> +#define CQSPI_INST_TYPE_OCTAL 3
>
> #define CQSPI_DUMMY_CLKS_PER_BYTE 8
> #define CQSPI_DUMMY_BYTES_MAX 4
> @@ -898,6 +899,9 @@ static int cqspi_set_protocol(struct spi_nor *nor, const int read)
> case SNOR_PROTO_1_1_4:
> f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
> break;
> + case SNOR_PROTO_1_1_8:
> + f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
> + break;
> default:
> return -EINVAL;
> }
> @@ -1205,6 +1209,7 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
> SNOR_HWCAPS_READ_FAST |
> SNOR_HWCAPS_READ_1_1_2 |
> SNOR_HWCAPS_READ_1_1_4 |
> + SNOR_HWCAPS_READ_1_1_8 |
Is this really supported on qspi versions of this IP? I guess not given
the description in the commit message and the name of the new
compatible (ospi instead of qspi).
> SNOR_HWCAPS_PP,
> };
> struct platform_device *pdev = cqspi->pdev;
> @@ -1456,6 +1461,10 @@ static const struct of_device_id cqspi_dt_ids[] = {
> .compatible = "ti,k2g-qspi",
> .data = (void *)CQSPI_NEEDS_WR_DELAY,
> },
> + {
> + .compatible = "ti,am654-ospi",
> + .data = (void *)CQSPI_NEEDS_WR_DELAY,
> + },
> { /* end of table */ }
> };
>
next prev parent reply other threads:[~2018-12-10 8:45 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-03 16:56 [PATCH 0/3] spi-nor: Add Octal SPI support Vignesh R
2018-10-03 16:56 ` [PATCH 1/3] mtd: spi-nor: Add Octal mode support for mt35xu512aba Vignesh R
2018-10-04 6:51 ` Yogesh Narayan Gaur
2018-10-04 7:39 ` Boris Brezillon
2018-10-04 8:47 ` Yogesh Narayan Gaur
2018-10-04 9:10 ` Boris Brezillon
2018-10-04 10:38 ` Vignesh R
2018-10-04 9:45 ` Boris Brezillon
2018-10-04 11:12 ` Vignesh R
2018-10-04 11:27 ` Boris Brezillon
2018-10-03 16:56 ` [PATCH 2/3] dt-bindings: cadence-quadspi: Add new compatible for AM654 SoC Vignesh R
2018-10-15 19:11 ` Rob Herring
2018-10-03 16:56 ` [PATCH 3/3] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller Vignesh R
2018-12-10 8:45 ` Boris Brezillon [this message]
2018-12-10 11:19 ` Vignesh R
2018-12-10 11:28 ` Boris Brezillon
2018-10-03 19:20 ` [PATCH 0/3] spi-nor: Add Octal SPI support Boris Brezillon
2018-10-04 10:35 ` Vignesh R
2018-10-04 11:17 ` Boris Brezillon
2018-10-08 15:36 ` Vignesh R
2018-10-12 8:52 ` Boris Brezillon
2018-12-09 8:47 ` Vignesh R
2018-12-10 8:45 ` Boris Brezillon
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20181210094513.6282d55e@bbrezillon \
--to=boris.brezillon@bootlin.com \
--cc=computersforpeace@gmail.com \
--cc=devicetree@vger.kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mtd@lists.infradead.org \
--cc=marek.vasut@gmail.com \
--cc=robh+dt@kernel.org \
--cc=vigneshr@ti.com \
--cc=yogeshnarayan.gaur@nxp.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).