From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH v3 3/6] media: sun6i: Set 300MHz mod clock for A64 Date: Tue, 11 Dec 2018 16:44:27 +0100 Message-ID: <20181211154427.uekytnmp2wlgxwm2@flea> References: <20181210115246.8188-1-jagan@amarulasolutions.com> <20181210115246.8188-4-jagan@amarulasolutions.com> Reply-To: maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="faq7xos5ziv2e6ih" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Content-Disposition: inline In-Reply-To: <20181210115246.8188-4-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Jagan Teki Cc: Yong Deng , Mauro Carvalho Chehab , Rob Herring , Mark Rutland , Chen-Yu Tsai , linux-media-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi , linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org, Michael Trimarchi List-Id: devicetree@vger.kernel.org --faq7xos5ziv2e6ih Content-Type: text/plain; charset="UTF-8" Content-Disposition: inline On Mon, Dec 10, 2018 at 05:22:43PM +0530, Jagan Teki wrote: > The default CSI_SCLK seems unable to drive the sensor to capture > the image, so update it to working clock rate 300MHz for A64. > > Signed-off-by: Jagan Teki > --- > drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c > index bbe45e893722..4b872800b244 100644 > --- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c > +++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c > @@ -822,6 +822,11 @@ static int sun6i_csi_resource_request(struct sun6i_csi_dev *sdev, > return PTR_ERR(sdev->clk_mod); > } > > + /* A64 need 300MHz mod clock to operate properly */ > + if (of_device_is_compatible(pdev->dev.of_node, > + "allwinner,sun50i-a64-csi")) > + clk_set_rate_exclusive(sdev->clk_mod, 300000000); > + Where is that 300MHz coming from? You claim in your comment that it "operates properly", yet in your previous mail about this, you were saying that 1080p @30Hz is broken. Which one is it? Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com --faq7xos5ziv2e6ih--