From mboxrd@z Thu Jan 1 00:00:00 1970 From: Patrick Havelange Subject: [PATCH] ARM: dts: ls1021a: Add memory controller Date: Tue, 11 Dec 2018 16:48:34 +0100 Message-ID: <20181211154834.4489-1-patrick.havelange@essensium.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Shawn Guo , Li Yang , Rob Herring , Mark Rutland , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Borislav Petkov , Mauro Carvalho Chehab , linux-edac@vger.kernel.org Cc: matthew.weber@rockwellcollins.com, patrick.havelange@essensium.com, arnout.vandecappelle@essensium.com List-Id: devicetree@vger.kernel.org The LS1021A has a memory controller that supports EDAC. This commit adds an entry for it. Signed-off-by: Patrick Havelange --- arch/arm/boot/dts/ls1021a.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index bdd6e66a79ad..a877c32bff20 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -125,6 +125,13 @@ interrupt-parent = <&gic>; ranges; + ddr: memory-controller@1080000 { + compatible = "fsl,qoriq-memory-controller"; + reg = <0x0 0x1080000 0x0 0x1000>; + interrupts = ; + big-endian; + }; + gic: interrupt-controller@1400000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; #interrupt-cells = <3>; -- 2.17.1