From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp.codeaurora.org ([198.145.29.96]:45286 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729671AbeLOKgU (ORCPT ); Sat, 15 Dec 2018 05:36:20 -0500 From: Govind Singh Subject: [PATCH v3 3/7] dt-bindings: clock: qcom: Add QCOM WCSS GCC clock bindings Date: Sat, 15 Dec 2018 16:05:53 +0530 Message-Id: <20181215103557.2748-4-govinds@codeaurora.org> In-Reply-To: <20181215103557.2748-1-govinds@codeaurora.org> References: <20181215103557.2748-1-govinds@codeaurora.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: devicetree-owner@vger.kernel.org To: bjorn.andersson@linaro.org, linux-remoteproc@vger.kernel.org, sboyd@kernel.org Cc: linux-clk@vger.kernel.org, sricharan@codeaurora.org, sibis@codeaurora.org, linux-arm-msm@vger.kernel.org, andy.gross@linaro.org, david.brown@linaro.org, linux-soc@vger.kernel.org, devicetree@vger.kernel.org, Govind Singh List-ID: Add device tree bindings for WiFi QDSP gcc clock controls found in QCS404 soc. Signed-off-by: Govind Singh Reviewed-by: Rob Herring --- include/dt-bindings/clock/qcom,gcc-qcs404.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h index 00ab0d77b38a..8f800adda225 100644 --- a/include/dt-bindings/clock/qcom,gcc-qcs404.h +++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h @@ -146,6 +146,8 @@ #define GCC_MDP_TBU_CLK 138 #define GCC_QDSS_DAP_CLK 139 #define GCC_DCC_XO_CLK 140 +#define GCC_WCSS_Q6_AHB_CBCR_CLK 141 +#define GCC_WCSS_Q6_AXIM_CBCR_CLK 142 #define GCC_GENI_IR_BCR 0 #define GCC_USB_HS_BCR 1 @@ -168,5 +170,6 @@ #define GCC_PCIE_0_CORE_STICKY_ARES 18 #define GCC_PCIE_0_SLEEP_ARES 19 #define GCC_PCIE_0_PIPE_ARES 20 +#define GCC_WDSP_RESTART 21 #endif -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project