From: Joseph Lo <josephl@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Jonathan Hunter <jonathanh@nvidia.com>
Cc: devicetree@vger.kernel.org, Rob Herring <robh@kernel.org>,
Stephen Boyd <sboyd@kernel.org>, Joseph Lo <josephl@nvidia.com>,
linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH V4 02/20] dt-bindings: clock: tegra124-dfll: add Tegra210 support
Date: Fri, 4 Jan 2019 11:06:44 +0800 [thread overview]
Message-ID: <20190104030702.8684-3-josephl@nvidia.com> (raw)
In-Reply-To: <20190104030702.8684-1-josephl@nvidia.com>
Add Tegra210 support for DFLL clock.
Cc: devicetree@vger.kernel.org
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
*V4:
- add more ack and RB tags
*V3:
- no change
*V2:
- add ack tag
---
.../devicetree/bindings/clock/nvidia,tegra124-dfll.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
index 5558bb5fcf2c..958e0ad78c52 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
@@ -10,7 +10,9 @@ control module that will automatically adjust the VDD_CPU voltage by
communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
Required properties:
-- compatible : should be "nvidia,tegra124-dfll"
+- compatible : should be one of:
+ - "nvidia,tegra124-dfll": for Tegra124
+ - "nvidia,tegra210-dfll": for Tegra210
- reg : Defines the following set of registers, in the order listed:
- registers for the DFLL control logic.
- registers for the I2C output logic.
--
2.20.1
next prev parent reply other threads:[~2019-01-04 3:06 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20190104030702.8684-1-josephl@nvidia.com>
2019-01-04 3:06 ` [PATCH V4 01/20] dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator Joseph Lo
2019-01-08 0:35 ` Joseph Lo
2019-01-11 8:14 ` Joseph Lo
2019-01-11 19:32 ` Rob Herring
2019-01-04 3:06 ` Joseph Lo [this message]
2019-01-04 3:06 ` [PATCH V4 03/20] dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required properties Joseph Lo
2019-01-04 3:06 ` [PATCH V4 04/20] dt-bindings: cpufreq: tegra124: remove cpu_lp clock " Joseph Lo
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