* [PATCH V5 1/4] dt-bindings: serial: lpuart: add imx8qxp compatible string [not found] <1545058517-18643-1-git-send-email-aisheng.dong@nxp.com> @ 2018-12-17 15:00 ` Aisheng Dong 2018-12-17 15:00 ` [PATCH V5 2/4] arm64: dts: imx: add imx8qxp support Aisheng Dong 2018-12-17 15:01 ` [PATCH V5 3/4] arm64: dts: imx: add imx8qxp mek support Aisheng Dong 2 siblings, 0 replies; 5+ messages in thread From: Aisheng Dong @ 2018-12-17 15:00 UTC (permalink / raw) To: linux-arm-kernel@lists.infradead.org Cc: Aisheng Dong, Mark Rutland, dongas86@gmail.com, devicetree@vger.kernel.org, catalin.marinas@arm.com, will.deacon@arm.com, Greg Kroah-Hartman, robh+dt@kernel.org, dl-linux-imx, kernel@pengutronix.de, linux-serial@vger.kernel.org, Fabio Estevam, shawnguo@kernel.org Add imx8qxp compatible string Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-serial@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> --- Documentation/devicetree/bindings/serial/fsl-lpuart.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt index 6bd3f2e..21483ba 100644 --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt @@ -8,6 +8,8 @@ Required properties: on LS1021A SoC with 32-bit big-endian register organization - "fsl,imx7ulp-lpuart" for lpuart compatible with the one integrated on i.MX7ULP SoC with 32-bit little-endian register organization + - "fsl,imx8qxp-lpuart" for lpuart compatible with the one integrated + on i.MX8QXP SoC with 32-bit little-endian register organization - reg : Address and length of the register set for the device - interrupts : Should contain uart interrupt - clocks : phandle + clock specifier pairs, one for each entry in clock-names -- 2.7.4 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH V5 2/4] arm64: dts: imx: add imx8qxp support [not found] <1545058517-18643-1-git-send-email-aisheng.dong@nxp.com> 2018-12-17 15:00 ` [PATCH V5 1/4] dt-bindings: serial: lpuart: add imx8qxp compatible string Aisheng Dong @ 2018-12-17 15:00 ` Aisheng Dong 2019-01-11 7:06 ` Shawn Guo 2018-12-17 15:01 ` [PATCH V5 3/4] arm64: dts: imx: add imx8qxp mek support Aisheng Dong 2 siblings, 1 reply; 5+ messages in thread From: Aisheng Dong @ 2018-12-17 15:00 UTC (permalink / raw) To: linux-arm-kernel@lists.infradead.org Cc: Aisheng Dong, Mark Rutland, dongas86@gmail.com, devicetree@vger.kernel.org, catalin.marinas@arm.com, will.deacon@arm.com, robh+dt@kernel.org, dl-linux-imx, kernel@pengutronix.de, Fabio Estevam, shawnguo@kernel.org i.MX 8QuadXPlus is a quad (4x) Cortex-A35 proccessor with powerful graphic and multimedia features. This patch adds the core SoC dtsi file support. Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> --- v4->v5: * no changes v3->v4: * update to new power domain binding power domain subnodes removed from dts * add LPCG clock nodes * clock ID updated accordingly v2->v3: * add more SoC specific compatible string to IP nodes * move memory node into board dts * change pd reg value into hex * add more explanation about SoC in commit message * add external clocks * remove pmu compatible string which is not supported v1->v2: * mu binding usage update * no define for node address * do not use '_' for node name * drop 'fsl-' prefix for imx dtsi * no defines for unit address * generic node names * range map for 32bit register * separate board dts Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> --- Documentation/devicetree/bindings/arm/fsl.txt | 4 + arch/arm64/boot/dts/freescale/imx8-ca35.dtsi | 61 ++++ arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 409 ++++++++++++++++++++++++++ 3 files changed, 474 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8-ca35.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp.dtsi diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt index 7fbc424..9b5be3e 100644 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ b/Documentation/devicetree/bindings/arm/fsl.txt @@ -131,6 +131,10 @@ i.MX7ULP generic board Required root node properties: - compatible = "fsl,imx7ulp"; +i.MX8QXP generic board +Required root node properties: + - compatible = "fsl,imx8qxp"; + Freescale Vybrid Platform Device Tree Bindings ---------------------------------------------- diff --git a/arch/arm64/boot/dts/freescale/imx8-ca35.dtsi b/arch/arm64/boot/dts/freescale/imx8-ca35.dtsi new file mode 100644 index 0000000..c79e97a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ca35.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017~2018 NXP + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/{ + cpus { + #address-cells = <2>; + #size-cells = <0>; + + /* We have 1 clusters with 4 Cortex-A35 cores */ + A35_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi new file mode 100644 index 0000000..da99b6f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -0,0 +1,409 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +#include <dt-bindings/clock/imx8qxp-clock.h> +#include <dt-bindings/firmware/imx/rsrc.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/pads-imx8qxp.h> + +#include "imx8-ca35.dtsi" + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &adma_lpuart0; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ + }; + + xtal32k: clock-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xtal_24MHz"; + }; + + scu { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", "tx1", "tx2", "tx3", + "rx0", "rx1", "rx2", "rx3"; + mboxes = <&lsio_mu1 0 0 + &lsio_mu1 0 1 + &lsio_mu1 0 2 + &lsio_mu1 0 3 + &lsio_mu1 1 0 + &lsio_mu1 1 1 + &lsio_mu1 1 2 + &lsio_mu1 1 3>; + + clk: clock-controller { + compatible = "fsl,imx8qxp-clk"; + #clock-cells = <1>; + clocks = <&xtal32k &xtal24m>; + clock-names = "xtal_32KHz", "xtal_24Mhz"; + }; + + iomuxc: pinctrl { + compatible = "fsl,imx8qxp-iomuxc"; + }; + + pd: imx8qx-pd { + compatible = "fsl,imx8qxp-scu-pd"; + #power-domain-cells = <1>; + }; + }; + + adma_subsys: bus@59000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x59000000 0x0 0x59000000 0x2000000>; + + adma_lpcg: clock-controller@59000000 { + compatible = "fsl,imx8qxp-lpcg-adma"; + reg = <0x59000000 0x2000000>; + #clock-cells = <1>; + }; + + adma_lpuart0: serial@5a060000 { + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x5a060000 0x1000>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&adma_lpcg IMX8QXP_ADMA_LPCG_UART0_BAUD_CLK>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_UART_0>; + status = "disabled"; + }; + + adma_i2c0: i2c@5a800000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x5a800000 0x4000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&adma_lpcg IMX8QXP_ADMA_LPCG_I2C0_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_ADMA_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_0>; + status = "disabled"; + }; + + adma_i2c1: i2c@5a810000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x5a810000 0x4000>; + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&adma_lpcg IMX8QXP_ADMA_LPCG_I2C1_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_ADMA_I2C1_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_1>; + status = "disabled"; + }; + + adma_i2c2: i2c@5a820000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x5a820000 0x4000>; + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&adma_lpcg IMX8QXP_ADMA_LPCG_I2C2_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_ADMA_I2C2_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_2>; + status = "disabled"; + }; + + adma_i2c3: i2c@5a830000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x5a830000 0x4000>; + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&adma_lpcg IMX8QXP_ADMA_LPCG_I2C3_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_ADMA_I2C3_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_3>; + status = "disabled"; + }; + }; + + conn_subsys: bus@5b000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; + + conn_lpcg: clock-controller@5b200000 { + compatible = "fsl,imx8qxp-lpcg-conn"; + reg = <0x5b200000 0xb0000>; + #clock-cells = <1>; + }; + + usdhc1: mmc@5b010000 { + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x5b010000 0x10000>; + clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK>, + <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_PER_CLK>, + <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_HCLK>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QXP_CONN_SDHC0_CLK>; + assigned-clock-rates = <200000000>; + power-domains = <&pd IMX_SC_R_SDHC_0>; + status = "disabled"; + }; + + usdhc2: mmc@5b020000 { + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x5b020000 0x10000>; + clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC1_IPG_CLK>, + <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC1_PER_CLK>, + <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC1_HCLK>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QXP_CONN_SDHC1_CLK>; + assigned-clock-rates = <200000000>; + power-domains = <&pd IMX_SC_R_SDHC_1>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc3: mmc@5b030000 { + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x5b030000 0x10000>; + clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC2_IPG_CLK>, + <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC2_PER_CLK>, + <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC2_HCLK>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QXP_CONN_SDHC2_CLK>; + assigned-clock-rates = <200000000>; + power-domains = <&pd IMX_SC_R_SDHC_2>; + status = "disabled"; + }; + + fec1: ethernet@5b040000 { + compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; + reg = <0x5b040000 0x10000>; + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_ENET0_IPG_CLK>, + <&conn_lpcg IMX8QXP_CONN_LPCG_ENET0_AHB_CLK>, + <&conn_lpcg IMX8QXP_CONN_LPCG_ENET0_TX_CLK>, + <&conn_lpcg IMX8QXP_CONN_LPCG_ENET0_ROOT_CLK>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + power-domains = <&pd IMX_SC_R_ENET_0>; + status = "disabled"; + }; + + fec2: ethernet@5b050000 { + compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; + reg = <0x5b050000 0x10000>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_ENET1_IPG_CLK>, + <&conn_lpcg IMX8QXP_CONN_LPCG_ENET1_AHB_CLK>, + <&conn_lpcg IMX8QXP_CONN_LPCG_ENET1_TX_CLK>, + <&conn_lpcg IMX8QXP_CONN_LPCG_ENET1_ROOT_CLK>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + power-domains = <&pd IMX_SC_R_ENET_1>; + status = "disabled"; + }; + }; + + db_subsys: bus@5c000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; + + ddr_pmu0: pmu@5c020000 { + reg = <0x5c020000 0x10000>; + }; + }; + + lsio_subsys: bus@5d000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; + + lsio_lpcg: clock-controller@5d400000 { + compatible = "fsl,imx8qxp-lpcg-lsio"; + reg = <0x5d400000 0x400000>; + #clock-cells = <1>; + }; + + lsio_mu0: mailbox@5d1b0000 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + reg = <0x5d1b0000 0x10000>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <0>; + status = "disabled"; + }; + + lsio_mu1: mailbox@5d1c0000 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + reg = <0x5d1c0000 0x10000>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + }; + + lsio_mu3: mailbox@5d1e0000 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + reg = <0x5d1e0000 0x10000>; + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <0>; + status = "disabled"; + }; + + lsio_mu4: mailbox@5d1f0000 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + reg = <0x5d1f0000 0x10000>; + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <0>; + status = "disabled"; + }; + + lsio_gpio0: gpio@5d080000 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + reg = <0x5d080000 0x10000>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_0>; + }; + + lsio_gpio1: gpio@5d090000 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + reg = <0x5d090000 0x10000>; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_1>; + }; + + lsio_gpio2: gpio@5d0a0000 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + reg = <0x5d0a0000 0x10000>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_2>; + }; + + lsio_gpio3: gpio@5d0b0000 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + reg = <0x5d0b0000 0x10000>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_3>; + }; + + lsio_gpio4: gpio@5d0c0000 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + reg = <0x5d0c0000 0x10000>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_4>; + }; + + lsio_gpio5: gpio@5d0d0000 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + reg = <0x5d0d0000 0x10000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_5>; + }; + + lsio_gpio6: gpio@5d0e0000 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + reg = <0x5d0e0000 0x10000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_6>; + }; + + lsio_gpio7: gpio@5d0f0000 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + reg = <0x5d0f0000 0x10000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_7>; + }; + }; + + hsio_subsys: bus@5f000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5f000000 0x0 0x5f000000 0x1000000>; + }; +}; -- 2.7.4 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH V5 2/4] arm64: dts: imx: add imx8qxp support 2018-12-17 15:00 ` [PATCH V5 2/4] arm64: dts: imx: add imx8qxp support Aisheng Dong @ 2019-01-11 7:06 ` Shawn Guo 2019-01-11 10:32 ` Aisheng Dong 0 siblings, 1 reply; 5+ messages in thread From: Shawn Guo @ 2019-01-11 7:06 UTC (permalink / raw) To: Aisheng Dong Cc: Mark Rutland, devicetree@vger.kernel.org, dongas86@gmail.com, catalin.marinas@arm.com, will.deacon@arm.com, robh+dt@kernel.org, dl-linux-imx, kernel@pengutronix.de, Fabio Estevam, linux-arm-kernel@lists.infradead.org On Mon, Dec 17, 2018 at 03:00:56PM +0000, Aisheng Dong wrote: > i.MX 8QuadXPlus is a quad (4x) Cortex-A35 proccessor with powerful > graphic and multimedia features. This patch adds the core SoC dtsi > file support. > > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: devicetree@vger.kernel.org > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: Sascha Hauer <kernel@pengutronix.de> > Cc: Fabio Estevam <fabio.estevam@nxp.com> > Reviewed-by: Rob Herring <robh@kernel.org> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> > --- > v4->v5: > * no changes > v3->v4: > * update to new power domain binding > power domain subnodes removed from dts > * add LPCG clock nodes > * clock ID updated accordingly > v2->v3: > * add more SoC specific compatible string to IP nodes > * move memory node into board dts > * change pd reg value into hex > * add more explanation about SoC in commit message > * add external clocks > * remove pmu compatible string which is not supported > v1->v2: > * mu binding usage update > * no define for node address > * do not use '_' for node name > * drop 'fsl-' prefix for imx dtsi > * no defines for unit address > * generic node names > * range map for 32bit register > * separate board dts > > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> > --- > Documentation/devicetree/bindings/arm/fsl.txt | 4 + Please separate the bindings from dts patch. We are moving to json-schema format. The fsl.txt has been removed on my for-next branch, so you need to patch fsl.yaml instead. > arch/arm64/boot/dts/freescale/imx8-ca35.dtsi | 61 ++++ > arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 409 ++++++++++++++++++++++++++ > 3 files changed, 474 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx8-ca35.dtsi > create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp.dtsi > > diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt > index 7fbc424..9b5be3e 100644 > --- a/Documentation/devicetree/bindings/arm/fsl.txt > +++ b/Documentation/devicetree/bindings/arm/fsl.txt > @@ -131,6 +131,10 @@ i.MX7ULP generic board > Required root node properties: > - compatible = "fsl,imx7ulp"; > > +i.MX8QXP generic board > +Required root node properties: > + - compatible = "fsl,imx8qxp"; > + > Freescale Vybrid Platform Device Tree Bindings > ---------------------------------------------- > > diff --git a/arch/arm64/boot/dts/freescale/imx8-ca35.dtsi b/arch/arm64/boot/dts/freescale/imx8-ca35.dtsi > new file mode 100644 > index 0000000..c79e97a > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8-ca35.dtsi Can you explain it a bit in commit log why we need to have a separate imx8-ca35.dtsi? From naming of the file, it seems there are more imx8 dts files than just imx8qxp.dtsi that will include it? > @@ -0,0 +1,61 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017~2018 NXP > + */ > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/{ > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + /* We have 1 clusters with 4 Cortex-A35 cores */ > + A35_0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + next-level-cache = <&A35_L2>; > + }; > + > + A35_1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + reg = <0x0 0x1>; > + enable-method = "psci"; > + next-level-cache = <&A35_L2>; > + }; > + > + A35_2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + reg = <0x0 0x2>; > + enable-method = "psci"; > + next-level-cache = <&A35_L2>; > + }; > + > + A35_3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + reg = <0x0 0x3>; > + enable-method = "psci"; > + next-level-cache = <&A35_L2>; > + }; > + > + A35_L2: l2-cache0 { > + compatible = "cache"; > + }; > + }; > + > + pmu { > + compatible = "arm,armv8-pmuv3"; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > +}; > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > new file mode 100644 > index 0000000..da99b6f > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > @@ -0,0 +1,409 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017-2018 NXP > + * Dong Aisheng <aisheng.dong@nxp.com> > + */ > + > +#include <dt-bindings/clock/imx8qxp-clock.h> > +#include <dt-bindings/firmware/imx/rsrc.h> > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/pinctrl/pads-imx8qxp.h> > + > +#include "imx8-ca35.dtsi" > + > +/ { > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + aliases { > + serial0 = &adma_lpuart0; > + mmc0 = &usdhc1; > + mmc1 = &usdhc2; > + mmc2 = &usdhc3; Please keep them sort alphabetically in alias name. > + }; > + > + gic: interrupt-controller@51a00000 { > + compatible = "arm,gic-v3"; > + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ > + <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ > + #interrupt-cells = <3>; > + interrupt-controller; > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ > + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ > + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ > + }; > + > + xtal32k: clock-xtal32k { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <32768>; > + clock-output-names = "xtal_32KHz"; > + }; > + > + xtal24m: clock-xtal24m { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <24000000>; > + clock-output-names = "xtal_24MHz"; > + }; > + > + scu { > + compatible = "fsl,imx-scu"; > + mbox-names = "tx0", "tx1", "tx2", "tx3", > + "rx0", "rx1", "rx2", "rx3"; > + mboxes = <&lsio_mu1 0 0 > + &lsio_mu1 0 1 > + &lsio_mu1 0 2 > + &lsio_mu1 0 3 > + &lsio_mu1 1 0 > + &lsio_mu1 1 1 > + &lsio_mu1 1 2 > + &lsio_mu1 1 3>; > + > + clk: clock-controller { > + compatible = "fsl,imx8qxp-clk"; > + #clock-cells = <1>; > + clocks = <&xtal32k &xtal24m>; > + clock-names = "xtal_32KHz", "xtal_24Mhz"; > + }; > + > + iomuxc: pinctrl { > + compatible = "fsl,imx8qxp-iomuxc"; > + }; > + > + pd: imx8qx-pd { > + compatible = "fsl,imx8qxp-scu-pd"; > + #power-domain-cells = <1>; > + }; > + }; > + > + adma_subsys: bus@59000000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x59000000 0x0 0x59000000 0x2000000>; > + > + adma_lpcg: clock-controller@59000000 { > + compatible = "fsl,imx8qxp-lpcg-adma"; > + reg = <0x59000000 0x2000000>; > + #clock-cells = <1>; > + }; > + > + adma_lpuart0: serial@5a060000 { > + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; > + reg = <0x5a060000 0x1000>; > + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-parent = <&gic>; > + clocks = <&adma_lpcg IMX8QXP_ADMA_LPCG_UART0_BAUD_CLK>; > + clock-names = "ipg"; > + power-domains = <&pd IMX_SC_R_UART_0>; > + status = "disabled"; > + }; > + > + adma_i2c0: i2c@5a800000 { > + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; > + reg = <0x5a800000 0x4000>; > + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-parent = <&gic>; > + clocks = <&adma_lpcg IMX8QXP_ADMA_LPCG_I2C0_CLK>; > + clock-names = "per"; > + assigned-clocks = <&clk IMX8QXP_ADMA_I2C0_CLK>; > + assigned-clock-rates = <24000000>; > + power-domains = <&pd IMX_SC_R_I2C_0>; > + status = "disabled"; > + }; > + > + adma_i2c1: i2c@5a810000 { > + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; > + reg = <0x5a810000 0x4000>; > + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-parent = <&gic>; > + clocks = <&adma_lpcg IMX8QXP_ADMA_LPCG_I2C1_CLK>; > + clock-names = "per"; > + assigned-clocks = <&clk IMX8QXP_ADMA_I2C1_CLK>; > + assigned-clock-rates = <24000000>; > + power-domains = <&pd IMX_SC_R_I2C_1>; > + status = "disabled"; > + }; > + > + adma_i2c2: i2c@5a820000 { > + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; > + reg = <0x5a820000 0x4000>; > + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-parent = <&gic>; > + clocks = <&adma_lpcg IMX8QXP_ADMA_LPCG_I2C2_CLK>; > + clock-names = "per"; > + assigned-clocks = <&clk IMX8QXP_ADMA_I2C2_CLK>; > + assigned-clock-rates = <24000000>; > + power-domains = <&pd IMX_SC_R_I2C_2>; > + status = "disabled"; > + }; > + > + adma_i2c3: i2c@5a830000 { > + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; > + reg = <0x5a830000 0x4000>; > + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-parent = <&gic>; > + clocks = <&adma_lpcg IMX8QXP_ADMA_LPCG_I2C3_CLK>; > + clock-names = "per"; > + assigned-clocks = <&clk IMX8QXP_ADMA_I2C3_CLK>; > + assigned-clock-rates = <24000000>; > + power-domains = <&pd IMX_SC_R_I2C_3>; > + status = "disabled"; > + }; > + }; > + > + conn_subsys: bus@5b000000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; > + > + conn_lpcg: clock-controller@5b200000 { > + compatible = "fsl,imx8qxp-lpcg-conn"; > + reg = <0x5b200000 0xb0000>; > + #clock-cells = <1>; > + }; > + > + usdhc1: mmc@5b010000 { > + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x5b010000 0x10000>; > + clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK>, > + <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_PER_CLK>, > + <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_HCLK>; > + clock-names = "ipg", "per", "ahb"; > + assigned-clocks = <&clk IMX8QXP_CONN_SDHC0_CLK>; > + assigned-clock-rates = <200000000>; > + power-domains = <&pd IMX_SC_R_SDHC_0>; > + status = "disabled"; > + }; > + > + usdhc2: mmc@5b020000 { > + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x5b020000 0x10000>; > + clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC1_IPG_CLK>, > + <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC1_PER_CLK>, > + <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC1_HCLK>; > + clock-names = "ipg", "per", "ahb"; > + assigned-clocks = <&clk IMX8QXP_CONN_SDHC1_CLK>; > + assigned-clock-rates = <200000000>; > + power-domains = <&pd IMX_SC_R_SDHC_1>; > + fsl,tuning-start-tap = <20>; > + fsl,tuning-step= <2>; > + status = "disabled"; > + }; > + > + usdhc3: mmc@5b030000 { > + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x5b030000 0x10000>; > + clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC2_IPG_CLK>, > + <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC2_PER_CLK>, > + <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC2_HCLK>; > + clock-names = "ipg", "per", "ahb"; > + assigned-clocks = <&clk IMX8QXP_CONN_SDHC2_CLK>; > + assigned-clock-rates = <200000000>; > + power-domains = <&pd IMX_SC_R_SDHC_2>; > + status = "disabled"; > + }; > + > + fec1: ethernet@5b040000 { > + compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; > + reg = <0x5b040000 0x10000>; > + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_ENET0_IPG_CLK>, > + <&conn_lpcg IMX8QXP_CONN_LPCG_ENET0_AHB_CLK>, > + <&conn_lpcg IMX8QXP_CONN_LPCG_ENET0_TX_CLK>, > + <&conn_lpcg IMX8QXP_CONN_LPCG_ENET0_ROOT_CLK>; > + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; > + fsl,num-tx-queues=<3>; > + fsl,num-rx-queues=<3>; > + power-domains = <&pd IMX_SC_R_ENET_0>; > + status = "disabled"; > + }; > + > + fec2: ethernet@5b050000 { > + compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; > + reg = <0x5b050000 0x10000>; > + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_ENET1_IPG_CLK>, > + <&conn_lpcg IMX8QXP_CONN_LPCG_ENET1_AHB_CLK>, > + <&conn_lpcg IMX8QXP_CONN_LPCG_ENET1_TX_CLK>, > + <&conn_lpcg IMX8QXP_CONN_LPCG_ENET1_ROOT_CLK>; > + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; > + fsl,num-tx-queues=<3>; > + fsl,num-rx-queues=<3>; > + power-domains = <&pd IMX_SC_R_ENET_1>; > + status = "disabled"; > + }; > + }; > + > + db_subsys: bus@5c000000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; > + > + ddr_pmu0: pmu@5c020000 { > + reg = <0x5c020000 0x10000>; > + }; How is it used? It doesn't even have a compatible. Shawn > + }; > + > + lsio_subsys: bus@5d000000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; > + > + lsio_lpcg: clock-controller@5d400000 { > + compatible = "fsl,imx8qxp-lpcg-lsio"; > + reg = <0x5d400000 0x400000>; > + #clock-cells = <1>; > + }; > + > + lsio_mu0: mailbox@5d1b0000 { > + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; > + reg = <0x5d1b0000 0x10000>; > + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; > + #mbox-cells = <0>; > + status = "disabled"; > + }; > + > + lsio_mu1: mailbox@5d1c0000 { > + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; > + reg = <0x5d1c0000 0x10000>; > + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; > + #mbox-cells = <2>; > + }; > + > + lsio_mu3: mailbox@5d1e0000 { > + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; > + reg = <0x5d1e0000 0x10000>; > + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; > + #mbox-cells = <0>; > + status = "disabled"; > + }; > + > + lsio_mu4: mailbox@5d1f0000 { > + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; > + reg = <0x5d1f0000 0x10000>; > + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; > + #mbox-cells = <0>; > + status = "disabled"; > + }; > + > + lsio_gpio0: gpio@5d080000 { > + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; > + reg = <0x5d080000 0x10000>; > + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + power-domains = <&pd IMX_SC_R_GPIO_0>; > + }; > + > + lsio_gpio1: gpio@5d090000 { > + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; > + reg = <0x5d090000 0x10000>; > + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + power-domains = <&pd IMX_SC_R_GPIO_1>; > + }; > + > + lsio_gpio2: gpio@5d0a0000 { > + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; > + reg = <0x5d0a0000 0x10000>; > + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + power-domains = <&pd IMX_SC_R_GPIO_2>; > + }; > + > + lsio_gpio3: gpio@5d0b0000 { > + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; > + reg = <0x5d0b0000 0x10000>; > + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + power-domains = <&pd IMX_SC_R_GPIO_3>; > + }; > + > + lsio_gpio4: gpio@5d0c0000 { > + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; > + reg = <0x5d0c0000 0x10000>; > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + power-domains = <&pd IMX_SC_R_GPIO_4>; > + }; > + > + lsio_gpio5: gpio@5d0d0000 { > + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; > + reg = <0x5d0d0000 0x10000>; > + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + power-domains = <&pd IMX_SC_R_GPIO_5>; > + }; > + > + lsio_gpio6: gpio@5d0e0000 { > + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; > + reg = <0x5d0e0000 0x10000>; > + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + power-domains = <&pd IMX_SC_R_GPIO_6>; > + }; > + > + lsio_gpio7: gpio@5d0f0000 { > + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; > + reg = <0x5d0f0000 0x10000>; > + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + power-domains = <&pd IMX_SC_R_GPIO_7>; > + }; > + }; > + > + hsio_subsys: bus@5f000000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x5f000000 0x0 0x5f000000 0x1000000>; > + }; > +}; > -- > 2.7.4 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH V5 2/4] arm64: dts: imx: add imx8qxp support 2019-01-11 7:06 ` Shawn Guo @ 2019-01-11 10:32 ` Aisheng Dong 0 siblings, 0 replies; 5+ messages in thread From: Aisheng Dong @ 2019-01-11 10:32 UTC (permalink / raw) To: Shawn Guo Cc: Mark Rutland, devicetree@vger.kernel.org, dongas86@gmail.com, catalin.marinas@arm.com, will.deacon@arm.com, robh+dt@kernel.org, dl-linux-imx, kernel@pengutronix.de, Fabio Estevam, linux-arm-kernel@lists.infradead.org Hi Shawn, Thanks for the review. > -----Original Message----- > From: Shawn Guo [mailto:shawnguo@kernel.org] > Sent: Friday, January 11, 2019 3:07 PM > On Mon, Dec 17, 2018 at 03:00:56PM +0000, Aisheng Dong wrote: > > i.MX 8QuadXPlus is a quad (4x) Cortex-A35 proccessor with powerful > > graphic and multimedia features. This patch adds the core SoC dtsi > > file support. > > > > Cc: Mark Rutland <mark.rutland@arm.com> > > Cc: devicetree@vger.kernel.org > > Cc: Shawn Guo <shawnguo@kernel.org> > > Cc: Sascha Hauer <kernel@pengutronix.de> > > Cc: Fabio Estevam <fabio.estevam@nxp.com> > > Reviewed-by: Rob Herring <robh@kernel.org> > > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> > > --- > > v4->v5: > > * no changes > > v3->v4: > > * update to new power domain binding > > power domain subnodes removed from dts > > * add LPCG clock nodes > > * clock ID updated accordingly > > v2->v3: > > * add more SoC specific compatible string to IP nodes > > * move memory node into board dts > > * change pd reg value into hex > > * add more explanation about SoC in commit message > > * add external clocks > > * remove pmu compatible string which is not supported > > v1->v2: > > * mu binding usage update > > * no define for node address > > * do not use '_' for node name > > * drop 'fsl-' prefix for imx dtsi > > * no defines for unit address > > * generic node names > > * range map for 32bit register > > * separate board dts > > > > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> > > --- > > Documentation/devicetree/bindings/arm/fsl.txt | 4 + > > Please separate the bindings from dts patch. We are moving to json-schema > format. The fsl.txt has been removed on my for-next branch, so you need to > patch fsl.yaml instead. > Got it > > arch/arm64/boot/dts/freescale/imx8-ca35.dtsi | 61 ++++ > > arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 409 > ++++++++++++++++++++++++++ > > 3 files changed, 474 insertions(+) > > create mode 100644 arch/arm64/boot/dts/freescale/imx8-ca35.dtsi > > create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp.dtsi > > > > diff --git a/Documentation/devicetree/bindings/arm/fsl.txt > > b/Documentation/devicetree/bindings/arm/fsl.txt > > index 7fbc424..9b5be3e 100644 > > --- a/Documentation/devicetree/bindings/arm/fsl.txt > > +++ b/Documentation/devicetree/bindings/arm/fsl.txt > > @@ -131,6 +131,10 @@ i.MX7ULP generic board Required root node > > properties: > > - compatible = "fsl,imx7ulp"; > > > > +i.MX8QXP generic board > > +Required root node properties: > > + - compatible = "fsl,imx8qxp"; > > + > > Freescale Vybrid Platform Device Tree Bindings > > ---------------------------------------------- > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8-ca35.dtsi > > b/arch/arm64/boot/dts/freescale/imx8-ca35.dtsi > > new file mode 100644 > > index 0000000..c79e97a > > --- /dev/null > > +++ b/arch/arm64/boot/dts/freescale/imx8-ca35.dtsi > > Can you explain it a bit in commit log why we need to have a separate > imx8-ca35.dtsi? From naming of the file, it seems there are more imx8 dts > files than just imx8qxp.dtsi that will include it? > I guess we could merge it into soc.dtsi. > > @@ -0,0 +1,61 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > > + * Copyright 2017~2018 NXP > > + */ > > + > > +#include <dt-bindings/interrupt-controller/arm-gic.h> > > + > > +/{ > > + cpus { > > + #address-cells = <2>; > > + #size-cells = <0>; > > + > > + /* We have 1 clusters with 4 Cortex-A35 cores */ > > + A35_0: cpu@0 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a35"; > > + reg = <0x0 0x0>; > > + enable-method = "psci"; > > + next-level-cache = <&A35_L2>; > > + }; > > + > > + A35_1: cpu@1 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a35"; > > + reg = <0x0 0x1>; > > + enable-method = "psci"; > > + next-level-cache = <&A35_L2>; > > + }; > > + > > + A35_2: cpu@2 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a35"; > > + reg = <0x0 0x2>; > > + enable-method = "psci"; > > + next-level-cache = <&A35_L2>; > > + }; > > + > > + A35_3: cpu@3 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a35"; > > + reg = <0x0 0x3>; > > + enable-method = "psci"; > > + next-level-cache = <&A35_L2>; > > + }; > > + > > + A35_L2: l2-cache0 { > > + compatible = "cache"; > > + }; > > + }; > > + > > + pmu { > > + compatible = "arm,armv8-pmuv3"; > > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + > > + psci { > > + compatible = "arm,psci-1.0"; > > + method = "smc"; > > + }; > > +}; > > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > > b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > > new file mode 100644 > > index 0000000..da99b6f > > --- /dev/null > > +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > > @@ -0,0 +1,409 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > > + * Copyright 2017-2018 NXP > > + * Dong Aisheng <aisheng.dong@nxp.com> > > + */ > > + > > +#include <dt-bindings/clock/imx8qxp-clock.h> > > +#include <dt-bindings/firmware/imx/rsrc.h> #include > > +<dt-bindings/gpio/gpio.h> #include > > +<dt-bindings/pinctrl/pads-imx8qxp.h> > > + > > +#include "imx8-ca35.dtsi" > > + > > +/ { > > + interrupt-parent = <&gic>; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + aliases { > > + serial0 = &adma_lpuart0; > > + mmc0 = &usdhc1; > > + mmc1 = &usdhc2; > > + mmc2 = &usdhc3; > > Please keep them sort alphabetically in alias name. Got it. > > > + }; > > + > > + gic: interrupt-controller@51a00000 { > > + compatible = "arm,gic-v3"; > > + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ > > + <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) > */ > > + #interrupt-cells = <3>; > > + interrupt-controller; > > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + > > + timer { > > + compatible = "arm,armv8-timer"; > > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure > */ > > + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical > Non-Secure */ > > + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ > > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ > > + }; > > + > > + xtal32k: clock-xtal32k { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <32768>; > > + clock-output-names = "xtal_32KHz"; > > + }; > > + > > + xtal24m: clock-xtal24m { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <24000000>; > > + clock-output-names = "xtal_24MHz"; > > + }; > > + > > + scu { > > + compatible = "fsl,imx-scu"; > > + mbox-names = "tx0", "tx1", "tx2", "tx3", > > + "rx0", "rx1", "rx2", "rx3"; > > + mboxes = <&lsio_mu1 0 0 > > + &lsio_mu1 0 1 > > + &lsio_mu1 0 2 > > + &lsio_mu1 0 3 > > + &lsio_mu1 1 0 > > + &lsio_mu1 1 1 > > + &lsio_mu1 1 2 > > + &lsio_mu1 1 3>; > > + > > + clk: clock-controller { > > + compatible = "fsl,imx8qxp-clk"; > > + #clock-cells = <1>; > > + clocks = <&xtal32k &xtal24m>; > > + clock-names = "xtal_32KHz", "xtal_24Mhz"; > > + }; > > + > > + iomuxc: pinctrl { > > + compatible = "fsl,imx8qxp-iomuxc"; > > + }; > > + > > + pd: imx8qx-pd { > > + compatible = "fsl,imx8qxp-scu-pd"; > > + #power-domain-cells = <1>; > > + }; > > + }; > > + > > + adma_subsys: bus@59000000 { > > + compatible = "simple-bus"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0x59000000 0x0 0x59000000 0x2000000>; > > + > > + adma_lpcg: clock-controller@59000000 { > > + compatible = "fsl,imx8qxp-lpcg-adma"; > > + reg = <0x59000000 0x2000000>; > > + #clock-cells = <1>; > > + }; > > + > > + adma_lpuart0: serial@5a060000 { > > + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; > > + reg = <0x5a060000 0x1000>; > > + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-parent = <&gic>; > > + clocks = <&adma_lpcg > IMX8QXP_ADMA_LPCG_UART0_BAUD_CLK>; > > + clock-names = "ipg"; > > + power-domains = <&pd IMX_SC_R_UART_0>; > > + status = "disabled"; > > + }; > > + > > + adma_i2c0: i2c@5a800000 { > > + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; > > + reg = <0x5a800000 0x4000>; > > + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-parent = <&gic>; > > + clocks = <&adma_lpcg IMX8QXP_ADMA_LPCG_I2C0_CLK>; > > + clock-names = "per"; > > + assigned-clocks = <&clk IMX8QXP_ADMA_I2C0_CLK>; > > + assigned-clock-rates = <24000000>; > > + power-domains = <&pd IMX_SC_R_I2C_0>; > > + status = "disabled"; > > + }; > > + > > + adma_i2c1: i2c@5a810000 { > > + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; > > + reg = <0x5a810000 0x4000>; > > + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-parent = <&gic>; > > + clocks = <&adma_lpcg IMX8QXP_ADMA_LPCG_I2C1_CLK>; > > + clock-names = "per"; > > + assigned-clocks = <&clk IMX8QXP_ADMA_I2C1_CLK>; > > + assigned-clock-rates = <24000000>; > > + power-domains = <&pd IMX_SC_R_I2C_1>; > > + status = "disabled"; > > + }; > > + > > + adma_i2c2: i2c@5a820000 { > > + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; > > + reg = <0x5a820000 0x4000>; > > + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-parent = <&gic>; > > + clocks = <&adma_lpcg IMX8QXP_ADMA_LPCG_I2C2_CLK>; > > + clock-names = "per"; > > + assigned-clocks = <&clk IMX8QXP_ADMA_I2C2_CLK>; > > + assigned-clock-rates = <24000000>; > > + power-domains = <&pd IMX_SC_R_I2C_2>; > > + status = "disabled"; > > + }; > > + > > + adma_i2c3: i2c@5a830000 { > > + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; > > + reg = <0x5a830000 0x4000>; > > + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-parent = <&gic>; > > + clocks = <&adma_lpcg IMX8QXP_ADMA_LPCG_I2C3_CLK>; > > + clock-names = "per"; > > + assigned-clocks = <&clk IMX8QXP_ADMA_I2C3_CLK>; > > + assigned-clock-rates = <24000000>; > > + power-domains = <&pd IMX_SC_R_I2C_3>; > > + status = "disabled"; > > + }; > > + }; > > + > > + conn_subsys: bus@5b000000 { > > + compatible = "simple-bus"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; > > + > > + conn_lpcg: clock-controller@5b200000 { > > + compatible = "fsl,imx8qxp-lpcg-conn"; > > + reg = <0x5b200000 0xb0000>; > > + #clock-cells = <1>; > > + }; > > + > > + usdhc1: mmc@5b010000 { > > + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; > > + interrupt-parent = <&gic>; > > + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; > > + reg = <0x5b010000 0x10000>; > > + clocks = <&conn_lpcg > IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK>, > > + <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_PER_CLK>, > > + <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_HCLK>; > > + clock-names = "ipg", "per", "ahb"; > > + assigned-clocks = <&clk IMX8QXP_CONN_SDHC0_CLK>; > > + assigned-clock-rates = <200000000>; > > + power-domains = <&pd IMX_SC_R_SDHC_0>; > > + status = "disabled"; > > + }; > > + > > + usdhc2: mmc@5b020000 { > > + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; > > + interrupt-parent = <&gic>; > > + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; > > + reg = <0x5b020000 0x10000>; > > + clocks = <&conn_lpcg > IMX8QXP_CONN_LPCG_SDHC1_IPG_CLK>, > > + <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC1_PER_CLK>, > > + <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC1_HCLK>; > > + clock-names = "ipg", "per", "ahb"; > > + assigned-clocks = <&clk IMX8QXP_CONN_SDHC1_CLK>; > > + assigned-clock-rates = <200000000>; > > + power-domains = <&pd IMX_SC_R_SDHC_1>; > > + fsl,tuning-start-tap = <20>; > > + fsl,tuning-step= <2>; > > + status = "disabled"; > > + }; > > + > > + usdhc3: mmc@5b030000 { > > + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; > > + interrupt-parent = <&gic>; > > + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; > > + reg = <0x5b030000 0x10000>; > > + clocks = <&conn_lpcg > IMX8QXP_CONN_LPCG_SDHC2_IPG_CLK>, > > + <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC2_PER_CLK>, > > + <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC2_HCLK>; > > + clock-names = "ipg", "per", "ahb"; > > + assigned-clocks = <&clk IMX8QXP_CONN_SDHC2_CLK>; > > + assigned-clock-rates = <200000000>; > > + power-domains = <&pd IMX_SC_R_SDHC_2>; > > + status = "disabled"; > > + }; > > + > > + fec1: ethernet@5b040000 { > > + compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; > > + reg = <0x5b040000 0x10000>; > > + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_ENET0_IPG_CLK>, > > + <&conn_lpcg IMX8QXP_CONN_LPCG_ENET0_AHB_CLK>, > > + <&conn_lpcg IMX8QXP_CONN_LPCG_ENET0_TX_CLK>, > > + <&conn_lpcg IMX8QXP_CONN_LPCG_ENET0_ROOT_CLK>; > > + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; > > + fsl,num-tx-queues=<3>; > > + fsl,num-rx-queues=<3>; > > + power-domains = <&pd IMX_SC_R_ENET_0>; > > + status = "disabled"; > > + }; > > + > > + fec2: ethernet@5b050000 { > > + compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; > > + reg = <0x5b050000 0x10000>; > > + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_ENET1_IPG_CLK>, > > + <&conn_lpcg IMX8QXP_CONN_LPCG_ENET1_AHB_CLK>, > > + <&conn_lpcg IMX8QXP_CONN_LPCG_ENET1_TX_CLK>, > > + <&conn_lpcg IMX8QXP_CONN_LPCG_ENET1_ROOT_CLK>; > > + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; > > + fsl,num-tx-queues=<3>; > > + fsl,num-rx-queues=<3>; > > + power-domains = <&pd IMX_SC_R_ENET_1>; > > + status = "disabled"; > > + }; > > + }; > > + > > + db_subsys: bus@5c000000 { > > + compatible = "simple-bus"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; > > + > > + ddr_pmu0: pmu@5c020000 { > > + reg = <0x5c020000 0x10000>; > > + }; > > How is it used? It doesn't even have a compatible. > They're still not used. I could remove those unused nodes. Regards Dong Aisheng > Shawn > > > + }; > > + > > + lsio_subsys: bus@5d000000 { > > + compatible = "simple-bus"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; > > + > > + lsio_lpcg: clock-controller@5d400000 { > > + compatible = "fsl,imx8qxp-lpcg-lsio"; > > + reg = <0x5d400000 0x400000>; > > + #clock-cells = <1>; > > + }; > > + > > + lsio_mu0: mailbox@5d1b0000 { > > + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; > > + reg = <0x5d1b0000 0x10000>; > > + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; > > + #mbox-cells = <0>; > > + status = "disabled"; > > + }; > > + > > + lsio_mu1: mailbox@5d1c0000 { > > + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; > > + reg = <0x5d1c0000 0x10000>; > > + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; > > + #mbox-cells = <2>; > > + }; > > + > > + lsio_mu3: mailbox@5d1e0000 { > > + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; > > + reg = <0x5d1e0000 0x10000>; > > + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; > > + #mbox-cells = <0>; > > + status = "disabled"; > > + }; > > + > > + lsio_mu4: mailbox@5d1f0000 { > > + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; > > + reg = <0x5d1f0000 0x10000>; > > + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; > > + #mbox-cells = <0>; > > + status = "disabled"; > > + }; > > + > > + lsio_gpio0: gpio@5d080000 { > > + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; > > + reg = <0x5d080000 0x10000>; > > + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; > > + gpio-controller; > > + #gpio-cells = <2>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + power-domains = <&pd IMX_SC_R_GPIO_0>; > > + }; > > + > > + lsio_gpio1: gpio@5d090000 { > > + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; > > + reg = <0x5d090000 0x10000>; > > + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; > > + gpio-controller; > > + #gpio-cells = <2>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + power-domains = <&pd IMX_SC_R_GPIO_1>; > > + }; > > + > > + lsio_gpio2: gpio@5d0a0000 { > > + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; > > + reg = <0x5d0a0000 0x10000>; > > + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; > > + gpio-controller; > > + #gpio-cells = <2>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + power-domains = <&pd IMX_SC_R_GPIO_2>; > > + }; > > + > > + lsio_gpio3: gpio@5d0b0000 { > > + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; > > + reg = <0x5d0b0000 0x10000>; > > + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; > > + gpio-controller; > > + #gpio-cells = <2>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + power-domains = <&pd IMX_SC_R_GPIO_3>; > > + }; > > + > > + lsio_gpio4: gpio@5d0c0000 { > > + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; > > + reg = <0x5d0c0000 0x10000>; > > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; > > + gpio-controller; > > + #gpio-cells = <2>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + power-domains = <&pd IMX_SC_R_GPIO_4>; > > + }; > > + > > + lsio_gpio5: gpio@5d0d0000 { > > + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; > > + reg = <0x5d0d0000 0x10000>; > > + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; > > + gpio-controller; > > + #gpio-cells = <2>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + power-domains = <&pd IMX_SC_R_GPIO_5>; > > + }; > > + > > + lsio_gpio6: gpio@5d0e0000 { > > + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; > > + reg = <0x5d0e0000 0x10000>; > > + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; > > + gpio-controller; > > + #gpio-cells = <2>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + power-domains = <&pd IMX_SC_R_GPIO_6>; > > + }; > > + > > + lsio_gpio7: gpio@5d0f0000 { > > + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; > > + reg = <0x5d0f0000 0x10000>; > > + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; > > + gpio-controller; > > + #gpio-cells = <2>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + power-domains = <&pd IMX_SC_R_GPIO_7>; > > + }; > > + }; > > + > > + hsio_subsys: bus@5f000000 { > > + compatible = "simple-bus"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0x5f000000 0x0 0x5f000000 0x1000000>; > > + }; > > +}; > > -- > > 2.7.4 > > > > > > _______________________________________________ > > linux-arm-kernel mailing list > > linux-arm-kernel@lists.infradead.org > > https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flist > > > s.infradead.org%2Fmailman%2Flistinfo%2Flinux-arm-kernel&data=02%7C > > > 01%7Caisheng.dong%40nxp.com%7Cd9d1fb2a24984eb79ad408d6779366c0 > %7C686ea > > > 1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636827872304455002& > sdata=EQ0 > > MbwoJ%2B0ftNgcIJbff55dOsRy0OUFPoCXztuikdjQ%3D&reserved=0 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH V5 3/4] arm64: dts: imx: add imx8qxp mek support [not found] <1545058517-18643-1-git-send-email-aisheng.dong@nxp.com> 2018-12-17 15:00 ` [PATCH V5 1/4] dt-bindings: serial: lpuart: add imx8qxp compatible string Aisheng Dong 2018-12-17 15:00 ` [PATCH V5 2/4] arm64: dts: imx: add imx8qxp support Aisheng Dong @ 2018-12-17 15:01 ` Aisheng Dong 2 siblings, 0 replies; 5+ messages in thread From: Aisheng Dong @ 2018-12-17 15:01 UTC (permalink / raw) To: linux-arm-kernel@lists.infradead.org Cc: Aisheng Dong, Mark Rutland, dongas86@gmail.com, devicetree@vger.kernel.org, catalin.marinas@arm.com, will.deacon@arm.com, robh+dt@kernel.org, dl-linux-imx, kernel@pengutronix.de, Fabio Estevam, shawnguo@kernel.org i.MX 8QuadXPlus is a quad (4x) Cortex-A35 proccessor with powerful graphic and multimedia features. This patch adds imx8qxp mek board support. Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> --- v4->v5: * change the dts compiling to depend on ARCH_MXC instead of SOC_IMX8QXP v3->v4: * remove un-documented enet phy properties v2->v3: * Pad names update * move memory node to here * add no-sd and no-sdio under emmc node --- Documentation/devicetree/bindings/arm/fsl.txt | 4 + arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 137 ++++++++++++++++++++++++++ 3 files changed, 142 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-mek.dts diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt index 9b5be3e..8e64985 100644 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ b/Documentation/devicetree/bindings/arm/fsl.txt @@ -105,6 +105,10 @@ i.MX7ULP Evaluation Kit Required root node properties: - compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp"; +i.MX8QXP MEK Board +Required root node properties: + - compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; + Generic i.MX boards ------------------- diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index f9be242..0db6e37 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -20,3 +20,4 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts new file mode 100644 index 0000000..03aad66 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017~2018 NXP + */ + +/dts-v1/; + +#include "imx8qxp.dtsi" + +/ { + model = "Freescale i.MX8QXP MEK"; + compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; + + chosen { + stdout-path = &adma_lpuart0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + }; + + reg_usdhc2_vmmc: usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&adma_lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 + IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; +}; -- 2.7.4 ^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2019-01-11 10:32 UTC | newest]
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[not found] <1545058517-18643-1-git-send-email-aisheng.dong@nxp.com>
2018-12-17 15:00 ` [PATCH V5 1/4] dt-bindings: serial: lpuart: add imx8qxp compatible string Aisheng Dong
2018-12-17 15:00 ` [PATCH V5 2/4] arm64: dts: imx: add imx8qxp support Aisheng Dong
2019-01-11 7:06 ` Shawn Guo
2019-01-11 10:32 ` Aisheng Dong
2018-12-17 15:01 ` [PATCH V5 3/4] arm64: dts: imx: add imx8qxp mek support Aisheng Dong
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