From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shawn Guo Subject: Re: [PATCH 1/2] soc: imx: gpcv2: handle additional power-down bits in handshake register Date: Fri, 11 Jan 2019 15:13:42 +0800 Message-ID: <20190111071341.GB32649@dragon> References: <20181217153152.21135-1-l.stach@pengutronix.de> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <20181217153152.21135-1-l.stach@pengutronix.de> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Lucas Stach Cc: devicetree@vger.kernel.org, patchwork-lst@pengutronix.de, Rob Herring , NXP Linux Team , Pengutronix Kernel Team , Fabio Estevam , linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org On Mon, Dec 17, 2018 at 04:31:51PM +0100, Lucas Stach wrote: > Some of the i.MX8MQ domains have an additional control bit in the PU > handshake (HSK) register. Documentation about this bit is a bit sparse > at the moment, but it seems that it controls a power-down request to > the AMBA domain bridge (ADB-400) attached to those domains. > > As the documentation doesn't desribe the usage of this bit yet, handle > it in the same way as done in the ATF implementation. > > Signed-off-by: Lucas Stach Applied both, thanks.