From mboxrd@z Thu Jan 1 00:00:00 1970 From: Borislav Petkov Subject: Re: [PATCH 2/2] EDAC: add ARM Cortex A15 L2 internal asynchronous error detection driver Date: Fri, 11 Jan 2019 19:29:44 +0100 Message-ID: <20190111182944.GA24304@zn.tnic> References: <20190108104204.GA14243@zn.tnic> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: James Morse Cc: "Wiebe, Wladislav (Nokia - DE/Ulm)" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "mchehab+samsung@kernel.org" , "gregkh@linuxfoundation.org" , "davem@davemloft.net" , "akpm@linux-foundation.org" , "nicolas.ferre@microchip.com" , "arnd@arndb.de" , "linux-edac@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "mchehab@kernel.org" , "Sverdlin, Alexander (Nokia - DE/Ulm)" , "devicetree@vger.kernel.org" List-Id: devicetree@vger.kernel.org On Fri, Jan 11, 2019 at 06:11:04PM +0000, James Morse wrote: > After I sent this it occurred to me the core can't know about errors in the L3 > cache (if there is one) or the memory-controller. These may have edac/ras > abilities, but they are selected by the soc integrator, so could be per soc. > This goes against Boris's no-per-functional-unit edac drivers. If we had to pick > one out of that set, I think the memory-controller is most useful as DRAM is the > most likely to be affected by errors. We have similar "designs" already :) Memory controller driver drivers/edac/fsl_ddr_edac.c gets linked together with: mpc85xx_edac_mod-y := fsl_ddr_edac.o mpc85xx_edac.o obj-$(CONFIG_EDAC_MPC85XX) += mpc85xx_edac_mod.o layerscape_edac_mod-y := fsl_ddr_edac.o layerscape_edac.o obj-$(CONFIG_EDAC_LAYERSCAPE) += layerscape_edac_mod.o -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.