From: Rob Herring <robh@kernel.org>
Cc: robh+dt@kernel.org, mark.rutland@arm.com, mperttunen@nvidia.com,
thierry.reding@gmail.com, jonathanh@nvidia.com,
adrian.hunter@intel.com, ulf.hansson@linaro.org,
anrao@nvidia.com, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-mmc@vger.kernel.org,
Sowjanya Komatineni <skomatineni@nvidia.com>
Subject: Re: [PATCH V4 1/3] dt-bindings: mmc: tegra: Add pinctrl for SDMMC drive strengths
Date: Tue, 15 Jan 2019 14:05:04 -0600 [thread overview]
Message-ID: <20190115200504.GA16841@bogus> (raw)
In-Reply-To: <1547160363-25323-1-git-send-email-skomatineni@nvidia.com>
On Thu, 10 Jan 2019 14:46:01 -0800, Sowjanya Komatineni wrote:
> Add pinctrls for 3V3 and 1V8 pad drive strength configuration for
> Tegra210 sdmmc.
>
> Tegra210 sdmmc has pad configuration registers in pinmux register
> domain and handled thru pinctrl to pinmux device node.
>
> Tegra186 and Tegra194 has pad configuration register with in the
> SDMMC register domain itself and are handles thru drive strength
> properties in sdmmc device node.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
next prev parent reply other threads:[~2019-01-15 20:05 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-10 22:46 [PATCH V4 1/3] dt-bindings: mmc: tegra: Add pinctrl for SDMMC drive strengths Sowjanya Komatineni
2019-01-10 22:46 ` [PATCH V4 2/3] arm64: dts: tegra: Add SDMMC Auto-cal settings Sowjanya Komatineni
2019-01-22 7:47 ` Ulf Hansson
2019-01-10 22:46 ` [PATCH V4 3/3] mmc: tegra: SDMMC pads auto-calibration Sowjanya Komatineni
2019-01-14 13:24 ` Adrian Hunter
2019-01-22 7:47 ` Ulf Hansson
2019-01-15 20:05 ` Rob Herring [this message]
2019-01-22 7:47 ` [PATCH V4 1/3] dt-bindings: mmc: tegra: Add pinctrl for SDMMC drive strengths Ulf Hansson
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