From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bjorn Andersson Subject: Re: [PATCH 12/13] arm64: dts: qcom: qcs404: Add cpufreq support Date: Wed, 16 Jan 2019 22:36:03 -0800 Message-ID: <20190117063603.GH25498@builder> References: <1545039990-19984-1-git-send-email-jorge.ramirez-ortiz@linaro.org> <1545039990-19984-13-git-send-email-jorge.ramirez-ortiz@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <1545039990-19984-13-git-send-email-jorge.ramirez-ortiz@linaro.org> Sender: linux-kernel-owner@vger.kernel.org To: Jorge Ramirez-Ortiz Cc: robh+dt@kernel.org, mark.rutland@arm.com, andy.gross@linaro.org, david.brown@linaro.org, sboyd@kernel.org, will.deacon@arm.com, mturquette@baylibre.com, jassisinghbrar@gmail.com, vkoul@kernel.org, niklas.cassel@linaro.org, sibis@codeaurora.org, georgi.djakov@linaro.org, arnd@arndb.de, horms+renesas@verge.net.au, heiko@sntech.de, enric.balletbo@collabora.com, jagan@amarulasolutions.com, olof@lixom.net, amit.kucheria@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org List-Id: devicetree@vger.kernel.org On Mon 17 Dec 01:46 PST 2018, Jorge Ramirez-Ortiz wrote: > Support CPU frequency scaling on qcs404. > Reviewed-by: Bjorn Andersson > Co-developed-by: Niklas Cassel > Signed-off-by: Niklas Cassel > Signed-off-by: Jorge Ramirez-Ortiz > --- > arch/arm64/boot/dts/qcom/qcs404.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi > index 2d9e70e..5a14887 100644 > --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi > @@ -30,6 +30,8 @@ > reg = <0x100>; > enable-method = "psci"; > next-level-cache = <&L2_0>; > + clocks = <&apcs_glb>; > + operating-points-v2 = <&cpu_opp_table>; > }; > > CPU1: cpu@101 { > @@ -38,6 +40,8 @@ > reg = <0x101>; > enable-method = "psci"; > next-level-cache = <&L2_0>; > + clocks = <&apcs_glb>; > + operating-points-v2 = <&cpu_opp_table>; > }; > > CPU2: cpu@102 { > @@ -46,6 +50,8 @@ > reg = <0x102>; > enable-method = "psci"; > next-level-cache = <&L2_0>; > + clocks = <&apcs_glb>; > + operating-points-v2 = <&cpu_opp_table>; > }; > > CPU3: cpu@103 { > @@ -54,6 +60,8 @@ > reg = <0x103>; > enable-method = "psci"; > next-level-cache = <&L2_0>; > + clocks = <&apcs_glb>; > + operating-points-v2 = <&cpu_opp_table>; > }; > > L2_0: l2-cache { > -- > 2.7.4 >