From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCH RESEND v1 4/4] dt-bindings: imx8-clock: add a53 and a72 clock id Date: Mon, 21 Jan 2019 18:10:11 -0600 Message-ID: <20190122001011.GA15952@bogus> References: <1547207400-28307-1-git-send-email-aisheng.dong@nxp.com> <1547207400-28307-5-git-send-email-aisheng.dong@nxp.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <1547207400-28307-5-git-send-email-aisheng.dong@nxp.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Aisheng Dong Cc: "devicetree@vger.kernel.org" , "sboyd@kernel.org" , "mturquette@baylibre.com" , dl-linux-imx , "kernel@pengutronix.de" , Fabio Estevam , "shawnguo@kernel.org" , "linux-clk@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" List-Id: devicetree@vger.kernel.org On Fri, Jan 11, 2019 at 11:56:09AM +0000, Aisheng Dong wrote: > Add a53 and a72 clock id, as there's still no users, we update > IMX_LSIO_MEM_CLK base to start from 6 to allow a53 and a72 clock > id to be continued with a35 clk. > > Cc: Stephen Boyd > Cc: Rob Herring > Cc: devicetree@vger.kernel.org > Cc: Shawn Guo > Cc: Sascha Hauer > Cc: Fabio Estevam > Cc: Michael Turquette > Signed-off-by: Dong Aisheng > --- > include/dt-bindings/clock/imx8-clock.h | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h > index 4236818..2f1aa2f 100644 > --- a/include/dt-bindings/clock/imx8-clock.h > +++ b/include/dt-bindings/clock/imx8-clock.h > @@ -13,10 +13,12 @@ > > /* CPU */ > #define IMX_A35_CLK 1 > +#define IMX_A53_CLK 2 > +#define IMX_A72_CLK 3 All 3 cores in one chip? If not maybe these should be split or define them as cpu cluster x clocks. > > /* LSIO SS */ > -#define IMX_LSIO_MEM_CLK 2 > -#define IMX_LSIO_BUS_CLK 3 > +#define IMX_LSIO_MEM_CLK 6 > +#define IMX_LSIO_BUS_CLK 7 > #define IMX_LSIO_PWM0_CLK 10 > #define IMX_LSIO_PWM1_CLK 11 > #define IMX_LSIO_PWM2_CLK 12 > -- > 2.7.4 >