From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Z.q. Hou" Subject: [PATCHv3 14/27] PCI: mobiveil: initialize Primary/Secondary/Subordinate bus number Date: Tue, 29 Jan 2019 08:09:58 +0000 Message-ID: <20190129080926.36773-15-Zhiqiang.Hou@nxp.com> References: <20190129080926.36773-1-Zhiqiang.Hou@nxp.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <20190129080926.36773-1-Zhiqiang.Hou@nxp.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" Cc: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" List-Id: devicetree@vger.kernel.org From: Hou Zhiqiang The reset value is all zero, so set a workable value for Primary, Secondary and Subordinate bus numbers. Signed-off-by: Hou Zhiqiang Reviewed-by: Minghuan Lian --- V3: - No change drivers/pci/controller/pcie-mobiveil.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controlle= r/pcie-mobiveil.c index db7ecb021c63..9210165fe8c0 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -582,6 +582,12 @@ static int mobiveil_host_init(struct mobiveil_pcie *pc= ie) u32 value, pab_ctrl, type; struct resource_entry *win; =20 + /* setup bus numbers */ + value =3D csr_readl(pcie, PCI_PRIMARY_BUS); + value &=3D 0xff000000; + value |=3D 0x00ff0100; + csr_writel(pcie, value, PCI_PRIMARY_BUS); + /* * program Bus Master Enable Bit in Command Register in PAB Config * Space --=20 2.17.1