* [PATCH v3 1/3] dt-bindings: PCI: dra7xx: Add SoC specific compatible strings
2019-01-24 8:29 [PATCH v3 0/3] PCI: dra7xx: Support PCIe x2 lane mode Kishon Vijay Abraham I
@ 2019-01-24 8:29 ` Kishon Vijay Abraham I
2019-01-24 8:29 ` [PATCH v3 2/3] dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7 Kishon Vijay Abraham I
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Kishon Vijay Abraham I @ 2019-01-24 8:29 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Lorenzo Pieralisi, Rob Herring
Cc: Bjorn Helgaas, Mark Rutland, linux-omap, linux-pci, devicetree,
linux-kernel, Sekhar Nori
Add new compatible strings for dra74x SoC (also used by dra76x) and
dra72x. This can be used to perform SoC specific configuration
(like configuring PCIe in x2 lane mode).
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/pci/ti-pci.txt | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt
index 452fe48c4fdd..e03d23631f5b 100644
--- a/Documentation/devicetree/bindings/pci/ti-pci.txt
+++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
@@ -1,8 +1,12 @@
TI PCI Controllers
PCIe DesignWare Controller
- - compatible: Should be "ti,dra7-pcie" for RC
- Should be "ti,dra7-pcie-ep" for EP
+ - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
+ Should be "ti,dra7-pcie-ep" for EP (deprecated)
+ Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
+ Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
+ Should be "ti,dra726-pcie-rc" for dra72x in RC mode
+ Should be "ti,dra726-pcie-ep" for dra72x in EP mode
- phys : list of PHY specifiers (used by generic PHY framework)
- phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
number of PHYs as specified in *phys* property.
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v3 3/3] PCI: dra7xx: Enable x2 mode support for dra74x, dra76x and dra72x
2019-01-24 8:29 [PATCH v3 0/3] PCI: dra7xx: Support PCIe x2 lane mode Kishon Vijay Abraham I
2019-01-24 8:29 ` [PATCH v3 1/3] dt-bindings: PCI: dra7xx: Add SoC specific compatible strings Kishon Vijay Abraham I
2019-01-24 8:29 ` [PATCH v3 2/3] dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7 Kishon Vijay Abraham I
@ 2019-01-24 8:29 ` Kishon Vijay Abraham I
2019-01-31 17:28 ` [PATCH v3 0/3] PCI: dra7xx: Support PCIe x2 lane mode Lorenzo Pieralisi
3 siblings, 0 replies; 6+ messages in thread
From: Kishon Vijay Abraham I @ 2019-01-24 8:29 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Lorenzo Pieralisi, Rob Herring
Cc: Bjorn Helgaas, Mark Rutland, linux-omap, linux-pci, devicetree,
linux-kernel
dra74x/dra76x and dra72x have separate compatible strings. Add support
for these compatible strings in pci-dra7xx driver to perform syscon
configurations required to get x2 mode working.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/controller/dwc/pci-dra7xx.c | 77 +++++++++++++++++++++++++
1 file changed, 77 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
index b4fbb4be212f..efb26096ccb5 100644
--- a/drivers/pci/controller/dwc/pci-dra7xx.c
+++ b/drivers/pci/controller/dwc/pci-dra7xx.c
@@ -81,6 +81,10 @@
#define MSI_REQ_GRANT BIT(0)
#define MSI_VECTOR_SHIFT 7
+#define PCIE_1LANE_2LANE_SELECTION BIT(13)
+#define PCIE_B1C0_MODE_SEL BIT(2)
+#define PCIE_B0_B1_TSYNCEN BIT(0)
+
struct dra7xx_pcie {
struct dw_pcie *pci;
void __iomem *base; /* DT ti_conf */
@@ -93,6 +97,7 @@ struct dra7xx_pcie {
struct dra7xx_pcie_of_data {
enum dw_pcie_device_mode mode;
+ u32 b1co_mode_sel_mask;
};
#define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev)
@@ -542,6 +547,26 @@ static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = {
.mode = DW_PCIE_EP_TYPE,
};
+static const struct dra7xx_pcie_of_data dra746_pcie_rc_of_data = {
+ .b1co_mode_sel_mask = BIT(2),
+ .mode = DW_PCIE_RC_TYPE,
+};
+
+static const struct dra7xx_pcie_of_data dra726_pcie_rc_of_data = {
+ .b1co_mode_sel_mask = GENMASK(3, 2),
+ .mode = DW_PCIE_RC_TYPE,
+};
+
+static const struct dra7xx_pcie_of_data dra746_pcie_ep_of_data = {
+ .b1co_mode_sel_mask = BIT(2),
+ .mode = DW_PCIE_EP_TYPE,
+};
+
+static const struct dra7xx_pcie_of_data dra726_pcie_ep_of_data = {
+ .b1co_mode_sel_mask = GENMASK(3, 2),
+ .mode = DW_PCIE_EP_TYPE,
+};
+
static const struct of_device_id of_dra7xx_pcie_match[] = {
{
.compatible = "ti,dra7-pcie",
@@ -551,6 +576,22 @@ static const struct of_device_id of_dra7xx_pcie_match[] = {
.compatible = "ti,dra7-pcie-ep",
.data = &dra7xx_pcie_ep_of_data,
},
+ {
+ .compatible = "ti,dra746-pcie-rc",
+ .data = &dra746_pcie_rc_of_data,
+ },
+ {
+ .compatible = "ti,dra726-pcie-rc",
+ .data = &dra726_pcie_rc_of_data,
+ },
+ {
+ .compatible = "ti,dra746-pcie-ep",
+ .data = &dra746_pcie_ep_of_data,
+ },
+ {
+ .compatible = "ti,dra726-pcie-ep",
+ .data = &dra726_pcie_ep_of_data,
+ },
{},
};
@@ -596,6 +637,34 @@ static int dra7xx_pcie_unaligned_memaccess(struct device *dev)
return ret;
}
+static int dra7xx_pcie_configure_two_lane(struct device *dev,
+ u32 b1co_mode_sel_mask)
+{
+ struct device_node *np = dev->of_node;
+ struct regmap *pcie_syscon;
+ unsigned int pcie_reg;
+ u32 mask;
+ u32 val;
+
+ pcie_syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-lane-sel");
+ if (IS_ERR(pcie_syscon)) {
+ dev_err(dev, "unable to get ti,syscon-lane-sel\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u32_index(np, "ti,syscon-lane-sel", 1,
+ &pcie_reg)) {
+ dev_err(dev, "couldn't get lane selection reg offset\n");
+ return -EINVAL;
+ }
+
+ mask = b1co_mode_sel_mask | PCIE_B0_B1_TSYNCEN;
+ val = PCIE_B1C0_MODE_SEL | PCIE_B0_B1_TSYNCEN;
+ regmap_update_bits(pcie_syscon, pcie_reg, mask, val);
+
+ return 0;
+}
+
static int __init dra7xx_pcie_probe(struct platform_device *pdev)
{
u32 reg;
@@ -616,6 +685,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
const struct of_device_id *match;
const struct dra7xx_pcie_of_data *data;
enum dw_pcie_device_mode mode;
+ u32 b1co_mode_sel_mask;
match = of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev);
if (!match)
@@ -623,6 +693,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
data = (struct dra7xx_pcie_of_data *)match->data;
mode = (enum dw_pcie_device_mode)data->mode;
+ b1co_mode_sel_mask = data->b1co_mode_sel_mask;
dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
if (!dra7xx)
@@ -678,6 +749,12 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
dra7xx->pci = pci;
dra7xx->phy_count = phy_count;
+ if (phy_count == 2) {
+ ret = dra7xx_pcie_configure_two_lane(dev, b1co_mode_sel_mask);
+ if (ret < 0)
+ dra7xx->phy_count = 1; /* Fallback to x1 lane mode */
+ }
+
ret = dra7xx_pcie_enable_phy(dra7xx);
if (ret) {
dev_err(dev, "failed to enable phy\n");
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v3 0/3] PCI: dra7xx: Support PCIe x2 lane mode
2019-01-24 8:29 [PATCH v3 0/3] PCI: dra7xx: Support PCIe x2 lane mode Kishon Vijay Abraham I
` (2 preceding siblings ...)
2019-01-24 8:29 ` [PATCH v3 3/3] PCI: dra7xx: Enable x2 mode support for dra74x, dra76x and dra72x Kishon Vijay Abraham I
@ 2019-01-31 17:28 ` Lorenzo Pieralisi
3 siblings, 0 replies; 6+ messages in thread
From: Lorenzo Pieralisi @ 2019-01-31 17:28 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Rob Herring, Bjorn Helgaas, Mark Rutland, linux-omap, linux-pci,
devicetree, linux-kernel
On Thu, Jan 24, 2019 at 01:59:54PM +0530, Kishon Vijay Abraham I wrote:
> Previous version of the patch series can be found here [1]
>
> Patch series adds support to enable x2 lane mode in dra74/dra76 and
> dra72 based boards in pci-dra7xx driver. It introduces new compatible
> strings in order to enable x2 lane mode support.
>
> Changes from v2:
> *) Have a single syscon dt property for configuring x2 lanes
> *) Fix minor comments given by Lorenzo (falling back to 1 lane mode,
> remove unused structure member).
>
> Changes from v1:
> *) Added ti prefix to syscon-lane-conf and syscon-lane-sel as
> suggested to Rob
> *) Merged "PCI: dwc: dra7xx: Add support for SoC specific compatible
> strings" and "PCI: dwc: pci-dra7xx: Enable x2 mode support" into
> a single patch.
> *) Fixed $subject as suggested by Bjorn
> *) Added x2 lane mode support for DRA72x
>
> The dts changes and phy changes will be sent as a separate series.
>
> [1] -> https://lkml.org/lkml/2017/12/19/175
>
> Kishon Vijay Abraham I (3):
> dt-bindings: PCI: dra7xx: Add SoC specific compatible strings
> dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7
> PCI: dra7xx: Enable x2 mode support for dra74x, dra76x and dra72x
>
> .../devicetree/bindings/pci/ti-pci.txt | 11 ++-
> drivers/pci/controller/dwc/pci-dra7xx.c | 77 +++++++++++++++++++
> 2 files changed, 86 insertions(+), 2 deletions(-)
I have applied the series to pci/dwc for v5.1, thanks.
Lorenzo
^ permalink raw reply [flat|nested] 6+ messages in thread