From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH 1/3] mmc: sunxi: Disable HS-DDR mode for H5 eMMC controller by default Date: Mon, 4 Feb 2019 10:32:14 +0100 Message-ID: <20190204093214.7zbomq5cddacdrmj@flea> References: <20190203155628.16767-1-wens@csie.org> <20190203155628.16767-2-wens@csie.org> Reply-To: maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="zfeanym3wm2ugnka" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Content-Disposition: inline In-Reply-To: <20190203155628.16767-2-wens-jdAy2FN1RRM@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Chen-Yu Tsai Cc: Ulf Hansson , linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, Chris Blake , stable-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org --zfeanym3wm2ugnka Content-Type: text/plain; charset="UTF-8" Content-Disposition: inline On Sun, Feb 03, 2019 at 11:56:26PM +0800, Chen-Yu Tsai wrote: > Some H5 boards seem to not have proper trace lengths for eMMC to be able > to use the default setting for the delay chains under HS-DDR mode. These > include the Bananapi M2+ H5 and NanoPi NEO Core2. However the Libre > Computer ALL-H3-CC-H5 works just fine. > > For the H5 (at least for now), default to not enabling HS-DDR modes in > the driver, and expect the device tree to signal HS-DDR capability on > boards that work. > > Reported-by: Chris Blake > Fixes: 07bafc1e3536 ("mmc: sunxi: Use new timing mode for A64 eMMC controller") > Cc: > Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com --zfeanym3wm2ugnka--