From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shawn Guo Subject: Re: [PATCH 2/2] ARM: dts: pfla02: add ksz9031 clock skew values Date: Mon, 11 Feb 2019 10:36:40 +0800 Message-ID: <20190211023639.GG22487@dragon> References: <20190204152956.13471-1-m.felsch@pengutronix.de> <20190204152956.13471-2-m.felsch@pengutronix.de> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <20190204152956.13471-2-m.felsch@pengutronix.de> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Marco Felsch Cc: devicetree@vger.kernel.org, Philipp Zabel , robh+dt@kernel.org, linux-imx@nxp.com, kernel@pengutronix.de, c.hemp@phytec.de, fabio.estevam@nxp.com, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org On Mon, Feb 04, 2019 at 04:29:56PM +0100, Marco Felsch wrote: > From: Philipp Zabel > > The pfla02 SoM has a Micrel KSZ9031RNX ethernet phy connected to the FEC, > which needs RX and TX clock skew settings to compensate for differences > in line length. The skew values are taken from barebox commit > 4c65c20f1071 ("ARM: pfla02: Set new ethernet phy tx timings"), which > is based on patches originally provided by Phytec: > > TX_CLK line is approx. 54mm longer than other TX lines which adds > a delay of 0.36ns. RGMII need a delay of min. 1.0ns. This mean we > have to add a delay of 0.64ns. We choose 0.78 to have a little gap. > This can be done by setting GTX pad skew value to 11100 > Also add a delay for the RX delay lines, needed for the Duallite > variant. => Set register 2.8 (RGMII Clock Pad Skew) to 0x039F. > > Cc: Christian Hemp > Signed-off-by: Philipp Zabel > Signed-off-by: Marco Felsch Applied, thanks.