From mboxrd@z Thu Jan 1 00:00:00 1970 From: Evan Green Subject: [PATCH v4 5/8] arm64: dts: msm8996: Add UFS PHY reset controller Date: Wed, 13 Feb 2019 15:25:23 -0800 Message-ID: <20190213232526.26995-6-evgreen@chromium.org> References: <20190213232526.26995-1-evgreen@chromium.org> Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <20190213232526.26995-1-evgreen@chromium.org> Sender: linux-kernel-owner@vger.kernel.org To: Andy Gross , Kishon Vijay Abraham I Cc: Stephen Boyd , Marc Gonzalez , Can Guo , Vivek Gautam , Douglas Anderson , Asutosh Das , Evan Green , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , David Brown , Mark Rutland List-Id: devicetree@vger.kernel.org Add the reset controller for the UFS controller, and wire it up so that the UFS PHY can initialize itself without relying on implicit sequencing between the two drivers. Signed-off-by: Evan Green Reviewed-by: Stephen Boyd --- Changes in v4: None Changes in v3: None Changes in v2: None arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 99b7495455a6..179f1988d45c 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -663,10 +663,11 @@ clock-names = "ref_clk_src", "ref_clk"; clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, <&gcc GCC_UFS_CLKREF_CLK>; + resets = <&ufshc 0>; status = "disabled"; }; - ufshc@624000 { + ufshc: ufshc@624000 { compatible = "qcom,ufshc"; reg = <0x624000 0x2500>; interrupts = ; @@ -722,6 +723,7 @@ <0 0>; lanes-per-direction = <1>; + #reset-cells = <1>; status = "disabled"; ufs_variant { -- 2.20.1