From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bjorn Andersson Subject: [PATCH v2 1/7] clk: gcc-qcs404: Add PCIe resets Date: Mon, 18 Feb 2019 22:04:01 -0800 Message-ID: <20190219060407.15263-2-bjorn.andersson@linaro.org> References: <20190219060407.15263-1-bjorn.andersson@linaro.org> Return-path: In-Reply-To: <20190219060407.15263-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org To: Michael Turquette , Stephen Boyd Cc: Andy Gross , David Brown , Bjorn Helgaas , Rob Herring , Mark Rutland , Kishon Vijay Abraham I , Stanimir Varbanov , Lorenzo Pieralisi , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org List-Id: devicetree@vger.kernel.org Enabling PCIe requires several of the PCIe related resets from GCC, so add them all. Reviewed-by: Niklas Cassel Acked-by: Stephen Boyd Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-qcs404.c | 7 +++++++ include/dt-bindings/clock/qcom,gcc-qcs404.h | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index 64da032bb9ed..5aed43923239 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -2675,6 +2675,13 @@ static const struct qcom_reset_map gcc_qcs404_resets[] = { [GCC_PCIE_0_PHY_BCR] = { 0x3e004 }, [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 }, [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c }, + [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6}, + [GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 }, + [GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 }, + [GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 }, + [GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 }, + [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 }, + [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 }, [GCC_EMAC_BCR] = { 0x4e000 }, }; diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h index 6ceb55ed72c6..00ab0d77b38a 100644 --- a/include/dt-bindings/clock/qcom,gcc-qcs404.h +++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h @@ -161,5 +161,12 @@ #define GCC_PCIE_0_LINK_DOWN_BCR 11 #define GCC_PCIEPHY_0_PHY_BCR 12 #define GCC_EMAC_BCR 13 +#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 14 +#define GCC_PCIE_0_AHB_ARES 15 +#define GCC_PCIE_0_AXI_SLAVE_ARES 16 +#define GCC_PCIE_0_AXI_MASTER_ARES 17 +#define GCC_PCIE_0_CORE_STICKY_ARES 18 +#define GCC_PCIE_0_SLEEP_ARES 19 +#define GCC_PCIE_0_PIPE_ARES 20 #endif -- 2.18.0