From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Baluta Subject: [PATCH v4 4/5] arm64: dts: imx8mq-evk: Enable SAI2 node Date: Wed, 27 Feb 2019 06:38:13 +0000 Message-ID: <20190227063737.24445-5-daniel.baluta@nxp.com> References: <20190227063737.24445-1-daniel.baluta@nxp.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <20190227063737.24445-1-daniel.baluta@nxp.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: "shawnguo@kernel.org" Cc: "S.j. Wang" , "angus@akkea.ca" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "l.stach@pengutronix.de" , Abel Vesa , "ccaione@baylibre.com" , "baruch@tkos.co.il" , "agx@sigxcpu.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , dl-linux-imx , Aisheng List-Id: devicetree@vger.kernel.org This sets up clock hierarchy and pin configuration. Use PLL1 to derive a proper rate for playing files with a rate multiple of 8000. Signed-off-by: Daniel Baluta --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot= /dts/freescale/imx8mq-evk.dts index 54737bf1772f..58de4a3d6029 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -52,6 +52,15 @@ }; }; =20 +&sai2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sai2>; + assigned-clocks =3D <&clk IMX8MQ_CLK_SAI2>; + assigned-clock-parents =3D <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates =3D <24576000>; + status =3D "okay"; +}; + &i2c1 { clock-frequency =3D <100000>; pinctrl-names =3D "default"; @@ -223,6 +232,16 @@ >; }; =20 + pinctrl_sai2: sai2grp { + fsl,pins =3D < + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins =3D < MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f --=20 2.17.1