From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paul Cercueil Subject: [PATCH v10 23/27] MIPS: CI20: Reduce system timer and clocksource to 3 MHz Date: Sat, 2 Mar 2019 20:34:09 -0300 Message-ID: <20190302233413.14813-24-paul@crapouillou.net> References: <20190302233413.14813-1-paul@crapouillou.net> Return-path: In-Reply-To: <20190302233413.14813-1-paul@crapouillou.net> Sender: linux-kernel-owner@vger.kernel.org To: Thierry Reding , Daniel Lezcano , Thomas Gleixner , Ralf Baechle , Paul Burton , James Hogan , Jonathan Corbet , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Mathieu Malaterre , od@zcrc.me, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-mips@vger.kernel.org, linux-doc@vger.kernel.org, linux-clk@vger.kernel.org, Paul Cercueil List-Id: devicetree@vger.kernel.org The default clock (48 MHz) is too fast for the system timer. Signed-off-by: Paul Cercueil Tested-by: Mathieu Malaterre Tested-by: Artur Rojek --- Notes: v5: New patch v6: Set also the rate for the clocksource channel's clock v7: No change v8: No change v9: Don't configure clock timer1, as the OS Timer is used as clocksource on this SoC v10: Revert back to v8 bahaviour. Let the user choose what clocksource should be used. arch/mips/boot/dts/ingenic/ci20.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index 4f7b1fa31cf5..30b01cfaaf5a 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -238,3 +238,9 @@ bias-disable; }; }; + +&tcu { + /* 3 MHz for the system timer and clocksource */ + assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>; + assigned-clock-rates = <3000000>, <3000000>; +}; -- 2.11.0