From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Z.q. Hou" Subject: [PATCHv4 21/28] PCI: mobiveil: add Byte and Half-Word width register accessors Date: Mon, 11 Mar 2019 09:32:49 +0000 Message-ID: <20190311093130.7209-22-Zhiqiang.Hou@nxp.com> References: <20190311093130.7209-1-Zhiqiang.Hou@nxp.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <20190311093130.7209-1-Zhiqiang.Hou@nxp.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" Cc: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" List-Id: devicetree@vger.kernel.org From: Hou Zhiqiang As there are some Byte and Half-Work width registers in PCIe configuration space, add Byte and Half-Word width register accessors. Signed-off-by: Hou Zhiqiang Reviewed-by: Minghuan Lian Reviewed-by: Subrahmanya Lingappa --- V4: - no change .../pci/controller/mobiveil/pcie-mobiveil.h | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/= controller/mobiveil/pcie-mobiveil.h index 81685840b378..933c2f34bc52 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h @@ -181,9 +181,29 @@ static inline u32 csr_readl(struct mobiveil_pcie *pcie= , u32 off) return csr_read(pcie, off, 0x4); } =20 +static inline u32 csr_readw(struct mobiveil_pcie *pcie, u32 off) +{ + return csr_read(pcie, off, 0x2); +} + +static inline u32 csr_readb(struct mobiveil_pcie *pcie, u32 off) +{ + return csr_read(pcie, off, 0x1); +} + static inline void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off= ) { csr_write(pcie, val, off, 0x4); } =20 +static inline void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32 off= ) +{ + csr_write(pcie, val, off, 0x2); +} + +static inline void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off= ) +{ + csr_write(pcie, val, off, 0x1); +} + #endif /* _PCIE_MOBIVEIL_H */ --=20 2.17.1