From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Baluta Subject: [PATCH] arm64: dts: imx8qxp: Add lpuart1/lpuart2/lpuart3 nodes Date: Sat, 30 Mar 2019 17:07:44 +0000 Message-ID: <20190330170725.24360-1-daniel.baluta@nxp.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: "shawnguo@kernel.org" Cc: "mark.rutland@arm.com" , Aisheng Dong , Peng Fan , Anson Huang , "devicetree@vger.kernel.org" , Teo Hall , Daniel Baluta , "s.hauer@pengutronix.de" , "linux-kernel@vger.kernel.org" , "robh+dt@kernel.org" , dl-linux-imx , "kernel@pengutronix.de" , "festevam@gmail.com" , "S.j. Wang" , "linux-arm-kernel@lists.infradead.org" List-Id: devicetree@vger.kernel.org lpuart nodes are part of the ADMA subsystem. See Audio DMA memory map in iMX8 QXP RM [1] This patch is based on the dtsi file initially submitted by Teo Hall in i.MX NXP internal tree. [1] https://www.nxp.com/docs/en/reference-manual/IMX8DQXPRM.pdf Signed-off-by: Teo Hall Signed-off-by: Daniel Baluta --- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 0cb939861a60..1adfe15c2ea5 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -193,6 +193,39 @@ status = "disabled"; }; + adma_lpuart1: serial@5a070000 { + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x5a070000 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_UART_1>; + status = "disabled"; + }; + + adma_lpuart2: serial@5a080000 { + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x5a080000 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_UART_2>; + status = "disabled"; + } + + adma_lpuart3: serial@5a090000 { + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x5a090000 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_UART_3>; + status = "disabled"; + } + adma_i2c0: i2c@5a800000 { compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x5a800000 0x4000>; -- 2.17.1