From mboxrd@z Thu Jan 1 00:00:00 1970 From: Miquel Raynal Subject: [PATCH 14/15] arm64: dts: marvell: Add 7k/8k PHYs in PCIe nodes Date: Mon, 1 Apr 2019 18:51:30 +0200 Message-ID: <20190401165131.23370-15-miquel.raynal@bootlin.com> References: <20190401165131.23370-1-miquel.raynal@bootlin.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20190401165131.23370-1-miquel.raynal@bootlin.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Kishon Vijay Abraham I Cc: devicetree@vger.kernel.org, Antoine Tenart , Russell King , Maxime Chevallier , Nadav Haklai , Rob Herring , Thomas Petazzoni , Miquel Raynal , linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org Fill-in the missing PCIe phys/phy-names DT properties of Armada 7k/8k based boards. The MacchiatoBin is a bit particular as the Armada8k-PCI IP supports x4 link widths and in this case the PHY for each lane must be referenced. Signed-off-by: Miquel Raynal --- arch/arm64/boot/dts/marvell/armada-7040-db.dts | 2 ++ .../boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 2 ++ arch/arm64/boot/dts/marvell/armada-8040-db.dts | 10 ++++++++++ arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 4 ++++ 4 files changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts index 09e1805565c8..131ce4229db0 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts @@ -96,6 +96,8 @@ &cp0_pcie2 { status = "okay"; + phys = <&cp0_comphy5 2>; + phy-names = "cp0-pcie2-x1-phy"; }; &cp0_i2c0 { diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts index 04e64743de14..b3716d206fbf 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts @@ -237,6 +237,8 @@ pinctrl-names = "default"; pinctrl-0 = <&cp0_pci0_reset_pins>; reset-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>; + phys = <&cp0_comphy0 0>; + phy-names = "cp0-pcie0-x1-phy"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts index 057af4ea2570..91c51188650a 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts @@ -111,11 +111,15 @@ /* CON6 on CP0 expansion */ &cp0_pcie0 { + phys = <&cp0_comphy0 0>; + phy-names = "cp0-pcie0-x1-phy"; status = "okay"; }; /* CON5 on CP0 expansion */ &cp0_pcie2 { + phys = <&cp0_comphy5 2>; + phy-names = "cp0-pcie2-x1-phy"; status = "okay"; }; @@ -201,16 +205,22 @@ /* CON6 on CP1 expansion */ &cp1_pcie0 { + phys = <&cp1_comphy0 0>; + phy-names = "cp1-pcie0-x1-phy"; status = "okay"; }; /* CON7 on CP1 expansion */ &cp1_pcie1 { + phys = <&cp1_comphy4 1>; + phy-names = "cp1-pcie1-x1-phy"; status = "okay"; }; /* CON5 on CP1 expansion */ &cp1_pcie2 { + phys = <&cp1_comphy5 2>; + phy-names = "cp1-pcie2-x1-phy"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi index f0ead11cc5fa..0639437ab4b4 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi @@ -184,6 +184,10 @@ num-lanes = <4>; num-viewport = <8>; reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>; + phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, + <&cp0_comphy2 0>, <&cp0_comphy3 0>; + phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy", + "cp0-pcie0-x4-lane2-phy", "cp0-pcie0-x4-lane3-phy"; status = "okay"; }; -- 2.19.1