From mboxrd@z Thu Jan 1 00:00:00 1970 From: Will Deacon Subject: Re: [PATCH V4 2/4] drivers/perf: imx_ddr: Add ddr performance counter support Date: Thu, 4 Apr 2019 12:17:14 +0100 Message-ID: <20190404111714.GA26392@fuggles.cambridge.arm.com> References: <1550253761-26841-1-git-send-email-Frank.Li@nxp.com> <1550253761-26841-2-git-send-email-Frank.Li@nxp.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <1550253761-26841-2-git-send-email-Frank.Li@nxp.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Frank Li Cc: "mark.rutland@arm.com" , Aisheng Dong , "devicetree@vger.kernel.org" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "robh+dt@kernel.org" , dl-linux-imx , "kernel@pengutronix.de" , "lznuaa@gmail.com" , "festevam@gmail.com" , "linux-arm-kernel@lists.infradead.org" List-Id: devicetree@vger.kernel.org Hi Frank, On Fri, Feb 15, 2019 at 06:03:11PM +0000, Frank Li wrote: > Add ddr performance monitor support for iMX8QXP > > There are 4 counters for ddr perfomance events. > counter 0 is dedicated for cycles. > you choose any up to 3 no cycles events. > > for example: > > perf stat -a -e ddr0/read-access/,ddr0/write-access/,ddr0/precharge/ ls > perf stat -a -e ddr0/cycles/,ddr0/read-access/,ddr0/write-access/ ls Could you elaborate a bit on DDR_CAP_AXI_ID, please? Specifically, how does the COUNTER_DPCR1 register work and what happens if I specify two simultaneous events with different values in config1? I'm a little wary of taking raw user input and throwing it straight into a device register! Will