From mboxrd@z Thu Jan  1 00:00:00 1970
From: Miquel Raynal <miquel.raynal@bootlin.com>
Subject: Re: [PATCH 3/3] ARM: dts: sunxi: Improve sun8i NAND transfers by
 using DMA
Date: Fri, 5 Apr 2019 11:38:18 +0200
Message-ID: <20190405113818.4dd5206b@xps13>
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To: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Mark Rutland <mark.rutland@arm.com>, devicetree@vger.kernel.org, Vignesh Raghavendra <vigneshr@ti.com>, Tudor Ambarus <Tudor.Ambarus@microchip.com>, Richard Weinberger <richard@nod.at>, Marek Vasut <marek.vasut@gmail.com>, Chen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>, linux-mtd@lists.infradead.org, Brian Norris <computersforpeace@gmail.com>, David Woodhouse <dwmw2@infradead.org>, linux-arm-kernel@lists.infradead.org
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Hi Maxime,

Maxime Ripard <maxime.ripard@bootlin.com> wrote on Fri, 5 Apr 2019
11:18:07 +0200:

> On Thu, Apr 04, 2019 at 06:21:11PM +0200, Miquel Raynal wrote:
> > In the current state, sun8i NAND controllers use PIO during
> > transfers. Throughput can be increased thanks to the use of DMA
> > (mostly during reads, because of the ECC pipelining feature).
> >
> > Besides the usual addition of DMA DT properties, because the sun8i =20
>=20
> The only thing that "sun8i" means for Allwinner is that the SoC has
> Cortex-A7 CPUs. You need to be more precise than that, why not just
> use A33?

I am always confused. I'll stick to A33 then.


Thanks,
Miqu=C3=A8l

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