From: Maxime Ripard <maxime.ripard@bootlin.com>
To: Rob Herring <robh@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Arnd Bergmann <arnd@arndb.de>,
Robin Murphy <robin.murphy@arm.com>,
dri-devel@lists.freedesktop.org,
Georgi Djakov <georgi.djakov@linaro.org>,
Paul Kocialkowski <paul.kocialkowski@bootlin.com>,
Chen-Yu Tsai <wens@csie.org>, Yong Deng <yong.deng@magewell.com>,
Frank Rowand <frowand.list@gmail.com>,
Dave Martin <dave.martin@arm.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v5 0/7] sunxi: Add DT representation for the MBUS controller
Date: Wed, 10 Apr 2019 16:34:44 +0200 [thread overview]
Message-ID: <20190410143444.tbuafcrqzbhwwsag@flea> (raw)
In-Reply-To: <20190410140128.GA6232@bogus>
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On Wed, Apr 10, 2019 at 09:01:28AM -0500, Rob Herring wrote:
> On Mon, Apr 08, 2019 at 10:11:26AM +0200, Maxime Ripard wrote:
> > On Sat, Apr 06, 2019 at 01:06:07AM -0500, Rob Herring wrote:
> > > On Mon, Apr 01, 2019 at 10:56:40AM +0200, Maxime Ripard wrote:
> > > > Hi,
> > > >
> > > > We've had for quite some time to hack around in our drivers to take into
> > > > account the fact that our DMA accesses are not done through the parent
> > > > node, but through another bus with a different mapping than the CPU for the
> > > > RAM (0 instead of 0x40000000 for most SoCs).
> > > >
> > > > After some discussion after the submission of a camera device suffering of
> > > > the same hacks, I've decided to put together a serie that introduce a
> > > > special interconnect name called "dma" that that allows to express the DMA
> > > > relationship between a master and its bus, even if they are not direct
> > > > parents in the DT.
> > > >
> > > > Let me know what you think,
> > > > Maxime
> > >
> > > LGTM.
> > >
> > > How do you propose merging this? I can take 1-5, and 6 and 7 thru
> > > arm-soc?
> >
> > You can merge 1-4, and I'll merge 5 through drm-misc and 6-7 through
> > arm-soc
>
> Done.
Thanks!
Applied 5, 6 and 7
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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prev parent reply other threads:[~2019-04-10 14:34 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-01 8:56 [PATCH v5 0/7] sunxi: Add DT representation for the MBUS controller Maxime Ripard
2019-04-01 8:56 ` [PATCH v5 1/7] dt-bindings: interconnect: Add a dma interconnect name Maxime Ripard
2019-04-01 8:56 ` [PATCH v5 2/7] dt-bindings: bus: Add binding for the Allwinner MBUS controller Maxime Ripard
2019-04-01 8:56 ` [PATCH v5 3/7] of: address: Retrieve a parent through a callback in __of_translate_address Maxime Ripard
2019-04-01 8:56 ` [PATCH v5 4/7] of: address: Add support for the parent DMA bus Maxime Ripard
2019-04-01 8:56 ` [PATCH v5 5/7] drm/sun4i: Rely on dma interconnect for our RAM offset Maxime Ripard
2019-04-01 8:56 ` [PATCH v5 6/7] clk: sunxi-ng: sun5i: Export the MBUS clock Maxime Ripard
2019-04-01 8:56 ` [PATCH v5 7/7] ARM: dts: sun5i: Add the MBUS controller Maxime Ripard
2019-04-06 6:06 ` [PATCH v5 0/7] sunxi: Add DT representation for " Rob Herring
2019-04-08 8:11 ` Maxime Ripard
2019-04-08 8:14 ` Chen-Yu Tsai
2019-04-08 8:21 ` Maxime Ripard
2019-04-08 8:26 ` Chen-Yu Tsai
2019-04-10 14:01 ` Rob Herring
2019-04-10 14:34 ` Maxime Ripard [this message]
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