From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Manikanta Maddireddy Subject: [PATCH V2 18/28] PCI: tegra: Program AFI_CACHE* registers only for Tegra20 Date: Tue, 23 Apr 2019 14:58:15 +0530 Message-ID: <20190423092825.759-19-mmaddireddy@nvidia.com> In-Reply-To: <20190423092825.759-1-mmaddireddy@nvidia.com> References: <20190423092825.759-1-mmaddireddy@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain To: thierry.reding@gmail.com, bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com, jonathanh@nvidia.com, lorenzo.pieralisi@arm.com, vidyas@nvidia.com Cc: linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manikanta Maddireddy List-ID: Cacheable upstream transactions are supported in Tegra20 and Tegra186 only. AFI_CACHE* registers are available in Tegra20 to support cacheable upstream transactions. In Tegra186, AFI_AXCACHE register is defined instead of AFI_CACHE* to be in line with its MSS design. Therefore, program AFI_CACHE* registers only for Tegra20. Signed-off-by: Manikanta Maddireddy --- V2: Used soc variable for comparision instead of compatible string. drivers/pci/controller/pci-tegra.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index f74930654443..9b841b0392ac 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -323,6 +323,7 @@ struct tegra_pcie_soc { bool program_deskew_time; bool raw_violation_fixup; bool update_fc_timer; + bool has_cache_bars; struct { struct { u32 rp_ectl_2_r1; @@ -932,11 +933,13 @@ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) afi_writel(pcie, 0, AFI_AXI_BAR5_SZ); afi_writel(pcie, 0, AFI_FPCI_BAR5); - /* map all upstream transactions as uncached */ - afi_writel(pcie, 0, AFI_CACHE_BAR0_ST); - afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ); - afi_writel(pcie, 0, AFI_CACHE_BAR1_ST); - afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ); + if (pcie->soc->has_cache_bars) { + /* map all upstream transactions as uncached */ + afi_writel(pcie, 0, AFI_CACHE_BAR0_ST); + afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ); + afi_writel(pcie, 0, AFI_CACHE_BAR1_ST); + afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ); + } /* MSI translations are setup only when needed */ afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST); -- 2.17.1