* [PATCH v4] clk: gcc-qcs404: Add PCIe resets
@ 2019-05-08 22:39 Bjorn Andersson
2019-05-09 12:51 ` Vinod Koul
2019-06-07 21:30 ` Stephen Boyd
0 siblings, 2 replies; 3+ messages in thread
From: Bjorn Andersson @ 2019-05-08 22:39 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Rob Herring, Mark Rutland, linux-arm-msm, linux-clk, linux-kernel,
devicetree
Enabling PCIe requires several of the PCIe related resets from GCC, so
add them all.
Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
Changes since v3:
- Fix rebase mistake in v2
Changes since v2:
- Rebase patch
drivers/clk/qcom/gcc-qcs404.c | 7 +++++++
include/dt-bindings/clock/qcom,gcc-qcs404.h | 7 +++++++
2 files changed, 14 insertions(+)
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index a54807eb3b28..29cf464dd2c8 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -2766,6 +2766,13 @@ static const struct qcom_reset_map gcc_qcs404_resets[] = {
[GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
[GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
+ [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6},
+ [GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 },
+ [GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 },
+ [GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 },
+ [GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 },
+ [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
+ [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
[GCC_EMAC_BCR] = { 0x4e000 },
};
diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h
index 454b3f43f538..2cd62c98561f 100644
--- a/include/dt-bindings/clock/qcom,gcc-qcs404.h
+++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h
@@ -166,5 +166,12 @@
#define GCC_PCIEPHY_0_PHY_BCR 12
#define GCC_EMAC_BCR 13
#define GCC_CDSP_RESTART 14
+#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 15
+#define GCC_PCIE_0_AHB_ARES 16
+#define GCC_PCIE_0_AXI_SLAVE_ARES 17
+#define GCC_PCIE_0_AXI_MASTER_ARES 18
+#define GCC_PCIE_0_CORE_STICKY_ARES 19
+#define GCC_PCIE_0_SLEEP_ARES 20
+#define GCC_PCIE_0_PIPE_ARES 21
#endif
--
2.18.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v4] clk: gcc-qcs404: Add PCIe resets
2019-05-08 22:39 [PATCH v4] clk: gcc-qcs404: Add PCIe resets Bjorn Andersson
@ 2019-05-09 12:51 ` Vinod Koul
2019-06-07 21:30 ` Stephen Boyd
1 sibling, 0 replies; 3+ messages in thread
From: Vinod Koul @ 2019-05-09 12:51 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
linux-arm-msm, linux-clk, linux-kernel, devicetree
On 08-05-19, 15:39, Bjorn Andersson wrote:
> Enabling PCIe requires several of the PCIe related resets from GCC, so
> add them all.
Reviewed-by: Vinod Koul <vkoul@kernel.org>
--
~Vinod
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v4] clk: gcc-qcs404: Add PCIe resets
2019-05-08 22:39 [PATCH v4] clk: gcc-qcs404: Add PCIe resets Bjorn Andersson
2019-05-09 12:51 ` Vinod Koul
@ 2019-06-07 21:30 ` Stephen Boyd
1 sibling, 0 replies; 3+ messages in thread
From: Stephen Boyd @ 2019-06-07 21:30 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette
Cc: Rob Herring, Mark Rutland, linux-arm-msm, linux-clk, linux-kernel,
devicetree
Quoting Bjorn Andersson (2019-05-08 15:39:22)
> Enabling PCIe requires several of the PCIe related resets from GCC, so
> add them all.
>
> Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Acked-by: Stephen Boyd <sboyd@kernel.org>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 3+ messages in thread
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