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Date: Thu, 9 May 2019 16:18:09 +0200
From: Thierry Reding <thierry.reding@gmail.com>
Subject: Re: [PATCH V2 08/28] PCI: tegra: Program UPHY electrical settings
 for Tegra210
Message-ID: <20190509141809.GH8907@ulmo>
References: <20190423092825.759-1-mmaddireddy@nvidia.com>
 <20190423092825.759-9-mmaddireddy@nvidia.com>
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In-Reply-To: <20190423092825.759-9-mmaddireddy@nvidia.com>
To: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Cc: bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com, jonathanh@nvidia.com, lorenzo.pieralisi@arm.com, vidyas@nvidia.com, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org
List-ID: <devicetree@vger.kernel.org>


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On Tue, Apr 23, 2019 at 02:58:05PM +0530, Manikanta Maddireddy wrote:
> UPHY electrical programming guidelines are documented in Tegra210 TRM.
> Program these electrical settings for proper eye diagram in Gen1 and Gen2
> link speeds.
>=20
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> V2: Addressed coding style comments
>=20
>  drivers/pci/controller/pci-tegra.c | 107 +++++++++++++++++++++++++++++
>  1 file changed, 107 insertions(+)

Acked-by: Thierry Reding <treding@nvidia.com>

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