* [PATCH 1/3] ARM: dts: imx7d: correct the pad drive strength setting
@ 2019-04-29 12:37 BOUGH CHEN
2019-04-29 12:38 ` [PATCH 2/3] ARM: dts: imx7d-sdb: add SD3.0 support for USDHC1 BOUGH CHEN
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: BOUGH CHEN @ 2019-04-29 12:37 UTC (permalink / raw)
To: robh+dt@kernel.org, mark.rutland@arm.com, shawnguo@kernel.org,
s.hauer@pengutronix.de
Cc: kernel@pengutronix.de, festevam@gmail.com, dl-linux-imx,
devicetree@vger.kernel.org
commit 5490c77d596a ("dt-bindings: pinctrl: imx7d: Fix PAD_CTL_DSE_X*")
point out that the PAD_CTL_DSE_X* values are wrongly document in the
RM. For the USDHC 100Mhz pad drive strength, it should be PAD_CTL_DSE_X4,
this patch fix this.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
arch/arm/boot/dts/imx7-colibri.dtsi | 22 +++++++++----------
arch/arm/boot/dts/imx7-mba7.dtsi | 10 ++++-----
arch/arm/boot/dts/imx7-tqma7.dtsi | 20 ++++++++---------
arch/arm/boot/dts/imx7d-pico.dtsi | 32 +++++++++++++--------------
arch/arm/boot/dts/imx7d-sdb.dts | 34 ++++++++++++++---------------
5 files changed, 59 insertions(+), 59 deletions(-)
diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi
index 895fbde4d433..b9d5dd35731b 100644
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -630,17 +630,17 @@
pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
fsl,pins = <
- MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
- MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
- MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x59
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x19
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
+ MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
>;
};
diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi
index 50abf18ad30b..9ecaabe7bcc7 100644
--- a/arch/arm/boot/dts/imx7-mba7.dtsi
+++ b/arch/arm/boot/dts/imx7-mba7.dtsi
@@ -437,12 +437,12 @@
pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
fsl,pins = <
- MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x59
MX7D_PAD_SD1_CLK__SD1_CLK 0x57
- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
>;
};
diff --git a/arch/arm/boot/dts/imx7-tqma7.dtsi b/arch/arm/boot/dts/imx7-tqma7.dtsi
index 9aaed85138cb..a3aa63b241e2 100644
--- a/arch/arm/boot/dts/imx7-tqma7.dtsi
+++ b/arch/arm/boot/dts/imx7-tqma7.dtsi
@@ -178,17 +178,17 @@
pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
fsl,pins = <
- MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x59
MX7D_PAD_SD3_CLK__SD3_CLK 0x51
- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
- MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
+ MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
>;
};
diff --git a/arch/arm/boot/dts/imx7d-pico.dtsi b/arch/arm/boot/dts/imx7d-pico.dtsi
index 6f50ebf31a0a..223092eae6c0 100644
--- a/arch/arm/boot/dts/imx7d-pico.dtsi
+++ b/arch/arm/boot/dts/imx7d-pico.dtsi
@@ -491,12 +491,12 @@
pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
fsl,pins = <
- MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
- MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x59
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x19
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
>;
};
@@ -541,16 +541,16 @@
pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
fsl,pins = <
- MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
- MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x59
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x19
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
>;
};
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index 202922ed3754..6a6035b2bc22 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -665,12 +665,12 @@
pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
fsl,pins = <
- MX7D_PAD_SD2_CMD__SD2_CMD 0x5a
- MX7D_PAD_SD2_CLK__SD2_CLK 0x1a
- MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
- MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a
- MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
- MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
+ MX7D_PAD_SD2_CMD__SD2_CMD 0x59
+ MX7D_PAD_SD2_CLK__SD2_CLK 0x19
+ MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
+ MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
+ MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
+ MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
>;
};
@@ -704,17 +704,17 @@
pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
fsl,pins = <
- MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
- MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
- MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x59
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x19
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
+ MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
>;
};
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 2/3] ARM: dts: imx7d-sdb: add SD3.0 support for USDHC1
2019-04-29 12:37 [PATCH 1/3] ARM: dts: imx7d: correct the pad drive strength setting BOUGH CHEN
@ 2019-04-29 12:38 ` BOUGH CHEN
2019-05-12 8:29 ` Shawn Guo
2019-04-29 12:38 ` [PATCH 3/3] ARM: dts: imx7s: set the tuning start tap for USDHC BOUGH CHEN
2019-05-12 8:28 ` [PATCH 1/3] ARM: dts: imx7d: correct the pad drive strength setting Shawn Guo
2 siblings, 1 reply; 5+ messages in thread
From: BOUGH CHEN @ 2019-04-29 12:38 UTC (permalink / raw)
To: robh+dt@kernel.org, mark.rutland@arm.com, shawnguo@kernel.org,
s.hauer@pengutronix.de
Cc: kernel@pengutronix.de, festevam@gmail.com, dl-linux-imx,
devicetree@vger.kernel.org
i.MX7D-SDB board support SD3.0 for USDHC1, so add it here.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
arch/arm/boot/dts/imx7d-sdb.dts | 53 +++++++++++++++++++++++++++++----
1 file changed, 48 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index 6a6035b2bc22..f468557c121b 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -87,6 +87,17 @@
regulator-max-microvolt = <1800000>;
};
+ reg_sd1_vmmc: regulator-sd1-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_SD1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <200000>;
+ enable-active-high;
+ };
+
+
reg_brcm: regulator-brcm {
compatible = "regulator-fixed";
gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
@@ -408,12 +419,16 @@
};
&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
wakeup-source;
keep-power-in-suspend;
+ vmmc-supply = <®_sd1_vmmc>;
+ fsl,tuning-step = <2>;
status = "okay";
};
@@ -638,6 +653,15 @@
>;
};
+ pinctrl_usdhc1_gpio: usdhc1_gpiogrp {
+ fsl,pins = <
+ MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
+ MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
+ MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* VMMC */
+ MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
@@ -646,9 +670,28 @@
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
- MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
- MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
- MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x59
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x19
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
>;
};
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 2/3] ARM: dts: imx7d-sdb: add SD3.0 support for USDHC1
2019-04-29 12:38 ` [PATCH 2/3] ARM: dts: imx7d-sdb: add SD3.0 support for USDHC1 BOUGH CHEN
@ 2019-05-12 8:29 ` Shawn Guo
0 siblings, 0 replies; 5+ messages in thread
From: Shawn Guo @ 2019-05-12 8:29 UTC (permalink / raw)
To: BOUGH CHEN
Cc: robh+dt@kernel.org, mark.rutland@arm.com, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com, dl-linux-imx,
devicetree@vger.kernel.org
On Mon, Apr 29, 2019 at 12:38:00PM +0000, BOUGH CHEN wrote:
> i.MX7D-SDB board support SD3.0 for USDHC1, so add it here.
>
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> ---
> arch/arm/boot/dts/imx7d-sdb.dts | 53 +++++++++++++++++++++++++++++----
> 1 file changed, 48 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
> index 6a6035b2bc22..f468557c121b 100644
> --- a/arch/arm/boot/dts/imx7d-sdb.dts
> +++ b/arch/arm/boot/dts/imx7d-sdb.dts
> @@ -87,6 +87,17 @@
> regulator-max-microvolt = <1800000>;
> };
>
> + reg_sd1_vmmc: regulator-sd1-vmmc {
> + compatible = "regulator-fixed";
> + regulator-name = "VDD_SD1";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
> + startup-delay-us = <200000>;
> + enable-active-high;
> + };
> +
> +
> reg_brcm: regulator-brcm {
> compatible = "regulator-fixed";
> gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
> @@ -408,12 +419,16 @@
> };
>
> &usdhc1 {
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_usdhc1>;
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
> cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
> wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
> wakeup-source;
> keep-power-in-suspend;
> + vmmc-supply = <®_sd1_vmmc>;
> + fsl,tuning-step = <2>;
> status = "okay";
> };
>
> @@ -638,6 +653,15 @@
> >;
> };
>
> + pinctrl_usdhc1_gpio: usdhc1_gpiogrp {
> + fsl,pins = <
> + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
> + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
> + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* VMMC */
> + MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */
The indentation of this line doesn't align with above ones.
Shawn
> + >;
> + };
> +
> pinctrl_usdhc1: usdhc1grp {
> fsl,pins = <
> MX7D_PAD_SD1_CMD__SD1_CMD 0x59
> @@ -646,9 +670,28 @@
> MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
> MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
> MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
> - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
> - MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
> - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
> + >;
> + };
> +
> + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
> + fsl,pins = <
> + MX7D_PAD_SD1_CMD__SD1_CMD 0x59
> + MX7D_PAD_SD1_CLK__SD1_CLK 0x19
> + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
> + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
> + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
> + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
> + >;
> + };
> +
> + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
> + fsl,pins = <
> + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
> + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
> + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
> + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
> + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
> + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
> >;
> };
>
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 3/3] ARM: dts: imx7s: set the tuning start tap for USDHC
2019-04-29 12:37 [PATCH 1/3] ARM: dts: imx7d: correct the pad drive strength setting BOUGH CHEN
2019-04-29 12:38 ` [PATCH 2/3] ARM: dts: imx7d-sdb: add SD3.0 support for USDHC1 BOUGH CHEN
@ 2019-04-29 12:38 ` BOUGH CHEN
2019-05-12 8:28 ` [PATCH 1/3] ARM: dts: imx7d: correct the pad drive strength setting Shawn Guo
2 siblings, 0 replies; 5+ messages in thread
From: BOUGH CHEN @ 2019-04-29 12:38 UTC (permalink / raw)
To: robh+dt@kernel.org, mark.rutland@arm.com, shawnguo@kernel.org,
s.hauer@pengutronix.de
Cc: kernel@pengutronix.de, festevam@gmail.com, dl-linux-imx,
devicetree@vger.kernel.org
For USDHC standard tuning method, i.MX7D require that the start tap
point must be larger than 10, otherwise the internal IC logic can't
work normal. So this patch set the tuning start tap as 20 according
to IC suggestion.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
arch/arm/boot/dts/imx7s.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 106711d2c01b..108652915f99 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -1126,6 +1126,7 @@
<&clks IMX7D_USDHC1_ROOT_CLK>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
+ fsl,tuning-start-tap = <20>;
status = "disabled";
};
@@ -1138,6 +1139,7 @@
<&clks IMX7D_USDHC2_ROOT_CLK>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
+ fsl,tuning-start-tap = <20>;
status = "disabled";
};
@@ -1150,6 +1152,7 @@
<&clks IMX7D_USDHC3_ROOT_CLK>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
+ fsl,tuning-start-tap = <20>;
status = "disabled";
};
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/3] ARM: dts: imx7d: correct the pad drive strength setting
2019-04-29 12:37 [PATCH 1/3] ARM: dts: imx7d: correct the pad drive strength setting BOUGH CHEN
2019-04-29 12:38 ` [PATCH 2/3] ARM: dts: imx7d-sdb: add SD3.0 support for USDHC1 BOUGH CHEN
2019-04-29 12:38 ` [PATCH 3/3] ARM: dts: imx7s: set the tuning start tap for USDHC BOUGH CHEN
@ 2019-05-12 8:28 ` Shawn Guo
2 siblings, 0 replies; 5+ messages in thread
From: Shawn Guo @ 2019-05-12 8:28 UTC (permalink / raw)
To: BOUGH CHEN
Cc: robh+dt@kernel.org, mark.rutland@arm.com, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com, dl-linux-imx,
devicetree@vger.kernel.org
On Mon, Apr 29, 2019 at 12:37:57PM +0000, BOUGH CHEN wrote:
> commit 5490c77d596a ("dt-bindings: pinctrl: imx7d: Fix PAD_CTL_DSE_X*")
> point out that the PAD_CTL_DSE_X* values are wrongly document in the
> RM. For the USDHC 100Mhz pad drive strength, it should be PAD_CTL_DSE_X4,
> this patch fix this.
>
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
I do not apply patches using base64 encoding.
Shawn
> ---
> arch/arm/boot/dts/imx7-colibri.dtsi | 22 +++++++++----------
> arch/arm/boot/dts/imx7-mba7.dtsi | 10 ++++-----
> arch/arm/boot/dts/imx7-tqma7.dtsi | 20 ++++++++---------
> arch/arm/boot/dts/imx7d-pico.dtsi | 32 +++++++++++++--------------
> arch/arm/boot/dts/imx7d-sdb.dts | 34 ++++++++++++++---------------
> 5 files changed, 59 insertions(+), 59 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi
> index 895fbde4d433..b9d5dd35731b 100644
> --- a/arch/arm/boot/dts/imx7-colibri.dtsi
> +++ b/arch/arm/boot/dts/imx7-colibri.dtsi
> @@ -630,17 +630,17 @@
>
> pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
> fsl,pins = <
> - MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
> - MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
> - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
> - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
> - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
> - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
> - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
> - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
> - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
> - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
> - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
> + MX7D_PAD_SD3_CMD__SD3_CMD 0x59
> + MX7D_PAD_SD3_CLK__SD3_CLK 0x19
> + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
> + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
> + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
> + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
> + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
> + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
> + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
> + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
> + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
> >;
> };
>
> diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi
> index 50abf18ad30b..9ecaabe7bcc7 100644
> --- a/arch/arm/boot/dts/imx7-mba7.dtsi
> +++ b/arch/arm/boot/dts/imx7-mba7.dtsi
> @@ -437,12 +437,12 @@
>
> pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
> fsl,pins = <
> - MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
> + MX7D_PAD_SD1_CMD__SD1_CMD 0x59
> MX7D_PAD_SD1_CLK__SD1_CLK 0x57
> - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
> - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
> - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
> - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
> + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
> + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
> + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
> + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
> >;
> };
>
> diff --git a/arch/arm/boot/dts/imx7-tqma7.dtsi b/arch/arm/boot/dts/imx7-tqma7.dtsi
> index 9aaed85138cb..a3aa63b241e2 100644
> --- a/arch/arm/boot/dts/imx7-tqma7.dtsi
> +++ b/arch/arm/boot/dts/imx7-tqma7.dtsi
> @@ -178,17 +178,17 @@
>
> pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
> fsl,pins = <
> - MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
> + MX7D_PAD_SD3_CMD__SD3_CMD 0x59
> MX7D_PAD_SD3_CLK__SD3_CLK 0x51
> - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
> - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
> - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
> - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
> - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
> - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
> - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
> - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
> - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
> + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
> + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
> + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
> + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
> + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
> + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
> + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
> + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
> + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
> >;
> };
>
> diff --git a/arch/arm/boot/dts/imx7d-pico.dtsi b/arch/arm/boot/dts/imx7d-pico.dtsi
> index 6f50ebf31a0a..223092eae6c0 100644
> --- a/arch/arm/boot/dts/imx7d-pico.dtsi
> +++ b/arch/arm/boot/dts/imx7d-pico.dtsi
> @@ -491,12 +491,12 @@
>
> pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
> fsl,pins = <
> - MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
> - MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
> - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
> - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
> - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
> - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
> + MX7D_PAD_SD1_CMD__SD1_CMD 0x59
> + MX7D_PAD_SD1_CLK__SD1_CLK 0x19
> + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
> + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
> + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
> + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
> MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
> >;
> };
> @@ -541,16 +541,16 @@
>
> pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
> fsl,pins = <
> - MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
> - MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
> - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
> - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
> - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
> - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
> - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
> - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
> - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
> - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
> + MX7D_PAD_SD3_CMD__SD3_CMD 0x59
> + MX7D_PAD_SD3_CLK__SD3_CLK 0x19
> + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
> + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
> + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
> + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
> + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
> + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
> + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
> + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
> >;
> };
>
> diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
> index 202922ed3754..6a6035b2bc22 100644
> --- a/arch/arm/boot/dts/imx7d-sdb.dts
> +++ b/arch/arm/boot/dts/imx7d-sdb.dts
> @@ -665,12 +665,12 @@
>
> pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
> fsl,pins = <
> - MX7D_PAD_SD2_CMD__SD2_CMD 0x5a
> - MX7D_PAD_SD2_CLK__SD2_CLK 0x1a
> - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
> - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a
> - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
> - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
> + MX7D_PAD_SD2_CMD__SD2_CMD 0x59
> + MX7D_PAD_SD2_CLK__SD2_CLK 0x19
> + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
> + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
> + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
> + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
> >;
> };
>
> @@ -704,17 +704,17 @@
>
> pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
> fsl,pins = <
> - MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
> - MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
> - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
> - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
> - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
> - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
> - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
> - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
> - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
> - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
> - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
> + MX7D_PAD_SD3_CMD__SD3_CMD 0x59
> + MX7D_PAD_SD3_CLK__SD3_CLK 0x19
> + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
> + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
> + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
> + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
> + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
> + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
> + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
> + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
> + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
> >;
> };
>
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2019-05-12 8:29 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-04-29 12:37 [PATCH 1/3] ARM: dts: imx7d: correct the pad drive strength setting BOUGH CHEN
2019-04-29 12:38 ` [PATCH 2/3] ARM: dts: imx7d-sdb: add SD3.0 support for USDHC1 BOUGH CHEN
2019-05-12 8:29 ` Shawn Guo
2019-04-29 12:38 ` [PATCH 3/3] ARM: dts: imx7s: set the tuning start tap for USDHC BOUGH CHEN
2019-05-12 8:28 ` [PATCH 1/3] ARM: dts: imx7d: correct the pad drive strength setting Shawn Guo
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