From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCH V6 10/15] dt-bindings: PHY: P2U: Add Tegra194 P2U block Date: Mon, 13 May 2019 10:22:05 -0500 Message-ID: <20190513152204.GA20594@bogus> References: <20190513050626.14991-1-vidyas@nvidia.com> <20190513050626.14991-11-vidyas@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20190513050626.14991-11-vidyas@nvidia.com> Sender: linux-kernel-owner@vger.kernel.org Cc: lorenzo.pieralisi@arm.com, bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com, thierry.reding@gmail.com, jonathanh@nvidia.com, kishon@ti.com, catalin.marinas@arm.com, will.deacon@arm.com, jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, mperttunen@nvidia.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kthota@nvidia.com, mmaddireddy@nvidia.com, vidyas@nvidia.com, sagar.tv@gmail.com List-Id: devicetree@vger.kernel.org On Mon, 13 May 2019 10:36:21 +0530, Vidya Sagar wrote: > Add support for Tegra194 P2U (PIPE to UPHY) module block which is a glue > module instantiated one for each PCIe lane between Synopsys DesignWare core > based PCIe IP and Universal PHY block. > > Signed-off-by: Vidya Sagar > --- > Changes since [v5]: > * Added Sob > * Changed node name from "p2u@xxxxxxxx" to "phy@xxxxxxxx" > > Changes since [v4]: > * None > > Changes since [v3]: > * None > > Changes since [v2]: > * Changed node label to reflect new format that includes either 'hsio' or > 'nvhs' in its name to reflect which UPHY brick they belong to > > Changes since [v1]: > * This is a new patch in v2 series > > .../bindings/phy/phy-tegra194-p2u.txt | 28 +++++++++++++++++++ > 1 file changed, 28 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt > Reviewed-by: Rob Herring