From: Rob Herring <robh@kernel.org>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
palmer@sifive.com, paul.walmsley@sifive.com,
linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu,
mark.rutland@arm.com, robh+dt@kernel.org,
sachin.ghadi@sifive.com, afd@ti.com,
Yash Shah <yash.shah@sifive.com>
Subject: Re: [PATCH v3 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller
Date: Mon, 13 May 2019 12:25:28 -0500 [thread overview]
Message-ID: <20190513172528.GA9362@bogus> (raw)
In-Reply-To: <1557139720-12384-2-git-send-email-yash.shah@sifive.com>
On Mon, 6 May 2019 16:18:39 +0530, Yash Shah wrote:
> Add device tree bindings for SiFive FU540 L2 cache controller driver
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> .../devicetree/bindings/riscv/sifive-l2-cache.txt | 51 ++++++++++++++++++++++
> 1 file changed, 51 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt
>
Reviewed-by: Rob Herring <robh@kernel.org>
next prev parent reply other threads:[~2019-05-13 17:25 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-06 10:48 [PATCH v3 0/2] L2 cache controller support for SiFive FU540 Yash Shah
2019-05-06 10:48 ` [PATCH v3 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller Yash Shah
2019-05-13 17:25 ` Rob Herring [this message]
2019-05-06 10:48 ` [PATCH v3 2/2] RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs Yash Shah
2019-05-06 12:18 ` Andrew F. Davis
2019-05-07 6:48 ` Yash Shah
2019-05-07 13:44 ` Andrew F. Davis
2019-05-08 5:49 ` Yash Shah
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