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From: Tony Lindgren <tony@atomide.com>
To: David Laight <David.Laight@ACULAB.COM>
Cc: "linux-omap@vger.kernel.org" <linux-omap@vger.kernel.org>,
	Dave Gerlach <d-gerlach@ti.com>, Faiz Abbas <faiz_abbas@ti.com>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Keerthy <j-keerthy@ti.com>, Nishanth Menon <nm@ti.com>,
	Peter Ujfalusi <peter.ujfalusi@ti.com>,
	Roger Quadros <rogerq@ti.com>, Suman Anna <s-anna@ti.com>,
	Tero Kristo <t-kristo@ti.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	Rob Herring <robh@kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: Re: [PATCH 01/12] bus: ti-sysc: Support 16-bit writes too
Date: Tue, 28 May 2019 05:27:22 -0700	[thread overview]
Message-ID: <20190528122722.GO5447@atomide.com> (raw)
In-Reply-To: <5e9a31dfdfd843469c51106fce9ea353@AcuMS.aculab.com>

* David Laight <David.Laight@ACULAB.COM> [190528 11:06]:
> From: Tony Lindgren
> > Sent: 27 May 2019 13:14
> > We need to also support 16-bit writes for i2c in addition to the reads
> > when we start configuring the sysconfig register for reset and idle modes.
> > 
> > Signed-off-by: Tony Lindgren <tony@atomide.com>
> > ---
> >  drivers/bus/ti-sysc.c | 7 +++++++
> >  1 file changed, 7 insertions(+)
> > 
> > diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c
> > --- a/drivers/bus/ti-sysc.c
> > +++ b/drivers/bus/ti-sysc.c
> > @@ -100,6 +100,13 @@ static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
> > 
> >  static void sysc_write(struct sysc *ddata, int offset, u32 value)
> >  {
> > +	if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
> > +		writew_relaxed(value & 0xffff, ddata->module_va + offset);
> > +		writew_relaxed(value >> 16, ddata->module_va + offset + 4);
> 
> Should that be + 2 ???

Well the stride for I2C revision registers is 4. But while checking
that again, I noticed that the other registers do not have HI and LO
registers and should just use a single 16-bit read and write. So far
it's harmless, but should be fixed.

Updated patch below.

Regards,

Tony

8< ----------------
>From tony Mon Sep 17 00:00:00 2001
From: Tony Lindgren <tony@atomide.com>
Date: Mon, 27 May 2019 04:51:53 -0700
Subject: [PATCH] bus: ti-sysc: Support 16-bit writes too

We need to also support 16-bit writes for i2c in addition to the reads
when we start configuring the sysconfig register for reset and idle modes.

Note that only i2c revision register has LO and HI registers, so let's
add a check also for 16-bit register read. This change is currently cosmetic
and does not affect anything until we enable the module specific quirk
handling for i2c reset and enable later on.

Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 drivers/bus/ti-sysc.c | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c
--- a/drivers/bus/ti-sysc.c
+++ b/drivers/bus/ti-sysc.c
@@ -100,6 +100,20 @@ static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
 
 static void sysc_write(struct sysc *ddata, int offset, u32 value)
 {
+	if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
+		writew_relaxed(value & 0xffff, ddata->module_va + offset);
+
+		/* Only i2c revision has LO and HI register with stride of 4 */
+		if (ddata->offsets[SYSC_REVISION] >= 0 &&
+		    offset == ddata->offsets[SYSC_REVISION]) {
+			u16 hi = value >> 16;
+
+			writew_relaxed(hi, ddata->module_va + offset + 4);
+		}
+
+		return;
+	}
+
 	writel_relaxed(value, ddata->module_va + offset);
 }
 
@@ -109,7 +123,14 @@ static u32 sysc_read(struct sysc *ddata, int offset)
 		u32 val;
 
 		val = readw_relaxed(ddata->module_va + offset);
-		val |= (readw_relaxed(ddata->module_va + offset + 4) << 16);
+
+		/* Only i2c revision has LO and HI register with stride of 4 */
+		if (ddata->offsets[SYSC_REVISION] >= 0 &&
+		    offset == ddata->offsets[SYSC_REVISION]) {
+			u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
+
+			val |= tmp << 16;
+		}
 
 		return val;
 	}
-- 
2.21.0

  reply	other threads:[~2019-05-28 12:27 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-27 12:13 [PATCH 00/12] ti-sysc driver changes to drop custom hwmods property Tony Lindgren
2019-05-27 12:13 ` [PATCH 01/12] bus: ti-sysc: Support 16-bit writes too Tony Lindgren
2019-05-28 11:06   ` David Laight
2019-05-28 12:27     ` Tony Lindgren [this message]
2019-05-27 12:13 ` [PATCH 02/12] bus: ti-sysc: Make OCP reset work for sysstatus and sysconfig reset bits Tony Lindgren
2019-05-27 12:13 ` [PATCH 03/12] bus: ti-sysc: Allow QUIRK_LEGACY_IDLE even if legacy_mode is not set Tony Lindgren
2019-05-27 12:13 ` [PATCH 04/12] bus: ti-sysc: Enable interconnect target module autoidle bit on enable Tony Lindgren
2019-05-27 12:13 ` [PATCH 05/12] bus: ti-sysc: Handle clockactivity for enable and disable Tony Lindgren
2019-05-27 12:13 ` [PATCH 06/12] bus: ti-sysc: Handle swsup idle mode quirks Tony Lindgren
2019-05-27 12:13 ` [PATCH 07/12] bus: ti-sysc: Set ENAWAKEUP if available Tony Lindgren
2019-05-27 12:13 ` [PATCH 08/12] bus: ti-sysc: Add support for disabling module without legacy mode Tony Lindgren
2019-05-27 12:13 ` [PATCH 09/12] bus: ti-sysc: Do rstctrl reset handling in two phases Tony Lindgren
2019-05-27 12:13 ` [PATCH 10/12] bus: ti-sysc: Detect uarts also on omap34xx Tony Lindgren
2019-05-27 12:13 ` [PATCH 11/12] ARM: dts: Drop legacy custom hwmods property for omap4 uart Tony Lindgren
2019-05-27 12:13 ` [PATCH 12/12] ARM: dts: Drop legacy custom hwmods property for omap4 mmc Tony Lindgren
2019-05-28  0:58 ` [PATCH 00/12] ti-sysc driver changes to drop custom hwmods property Keerthy
2019-05-28  6:16   ` Tony Lindgren

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