From mboxrd@z Thu Jan 1 00:00:00 1970 From: Joseph Lo Subject: [PATCH V4 1/8] dt-bindings: memory: tegra: Add external memory controller binding for Tegra210 Date: Wed, 29 May 2019 16:21:32 +0800 Message-ID: <20190529082139.5581-2-josephl@nvidia.com> References: <20190529082139.5581-1-josephl@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20190529082139.5581-1-josephl@nvidia.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Thierry Reding , Peter De Schrijver , Jonathan Hunter , Rob Herring , Stephen Boyd Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo List-Id: devicetree@vger.kernel.org Add the binding document for the external memory controller (EMC) which communicates with external LPDDR4 devices. It includes the bindings of the EMC node and a sub-node of EMC table which under the reserved memory node. The EMC table contains the data of the rates that EMC supported. Signed-off-by: Joseph Lo --- v4: - no change v3: - drop the bindings of EMC table - add memory-region and reserved-memory node for EMC table --- .../nvidia,tegra210-emc.txt | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt new file mode 100644 index 000000000000..d65aeef2329c --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt @@ -0,0 +1,55 @@ +NVIDIA Tegra210 SoC EMC (external memory controller) +==================================================== + +Device node +=========== +Required properties : +- compatible : should be "nvidia,tegra210-emc". +- reg : physical base address and length of the controller's registers. +- clocks : phandles of the possible source clocks. +- clock-names : names of the possible source clocks. +- interrupts : Should contain the EMC general interrupt. +- memory-region : phandle to the reserved memory (see + Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) which + contains a sub-node of EMC table. +- nvidia,memory-controller : phandle of the memory controller. + +Reserved memory node +==================== +Should contain a sub-node of EMC table with required properties: +- compatible : should be "nvidia,tegra210-emc-table". +- reg : physical address and length of the location of EMC table. + +Example: + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + emc_table: emc-table@8be00000 { + compatible = "nvidia,tegra210-emc-table"; + reg = <0x0 0x8be00000 0x0 0x10000>; + status = "okay"; + }; + }; + + external-memory-controller@7001b000 { + compatible = "nvidia,tegra210-emc"; + reg = <0x0 0x7001b000 0x0 0x1000>, + <0x0 0x7001e000 0x0 0x1000>, + <0x0 0x7001f000 0x0 0x1000>; + clocks = <&tegra_car TEGRA210_CLK_EMC>, + <&tegra_car TEGRA210_CLK_PLL_M>, + <&tegra_car TEGRA210_CLK_PLL_C>, + <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_CLK_M>, + <&tegra_car TEGRA210_CLK_PLL_M_UD>, + <&tegra_car TEGRA210_CLK_PLL_MB_UD>, + <&tegra_car TEGRA210_CLK_PLL_MB>, + <&tegra_car TEGRA210_CLK_PLL_P_UD>; + clock-names = "emc", "pll_m", "pll_c", "pll_p", "clk_m", + "pll_m_ud", "pll_mb_ud", "pll_mb", "pll_p_ud"; + interrupts = ; + memory-region = <&emc_table>; + nvidia,memory-controller = <&mc>; + }; -- 2.21.0