From: Stephen Boyd <sboyd@kernel.org>
To: jason@lakedaemon.net, jonathanh@nvidia.com,
linus.walleij@linaro.org, marc.zyngier@arm.com,
mark.rutland@arm.com, stefan@agner.ch, tglx@linutronix.de,
thierry.reding@gmail.com
Cc: pdeschrijver@nvidia.com, pgaikwad@nvidia.com,
linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org,
jckuo@nvidia.com, josephl@nvidia.com, talho@nvidia.com,
skomatineni@nvidia.com, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org, mperttunen@nvidia.com,
spatra@nvidia.com, robh+dt@kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH V2 03/12] clk: tegra: save and restore PLLs state for system
Date: Wed, 29 May 2019 16:28:09 -0700 [thread overview]
Message-ID: <20190529232810.14A5224366@mail.kernel.org> (raw)
In-Reply-To: <1559084936-4610-4-git-send-email-skomatineni@nvidia.com>
Quoting Sowjanya Komatineni (2019-05-28 16:08:47)
> This patch has implementation of saving and restoring PLL's state to
> support system suspend and resume operations.
Can you provide some more background on _why_ this patch should exist?
That's typically what gets written in the commit text.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> drivers/clk/tegra/clk-divider.c | 19 ++++++++
> drivers/clk/tegra/clk-pll-out.c | 25 +++++++++++
> drivers/clk/tegra/clk-pll.c | 99 ++++++++++++++++++++++++++++++++---------
> drivers/clk/tegra/clk.h | 9 ++++
> 4 files changed, 132 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
> index 2a1822a22740..718694727042 100644
> --- a/drivers/clk/tegra/clk-divider.c
> +++ b/drivers/clk/tegra/clk-divider.c
> @@ -14,6 +14,7 @@
> * along with this program. If not, see <http://www.gnu.org/licenses/>.
> */
>
> +#include <linux/clk.h>
> #include <linux/kernel.h>
> #include <linux/io.h>
> #include <linux/err.h>
> @@ -179,3 +180,21 @@ struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
> reg, 16, 1, CLK_DIVIDER_READ_ONLY,
> mc_div_table, lock);
> }
> +
> +#if defined(CONFIG_PM_SLEEP)
> +void tegra_clk_divider_resume(struct clk_hw *hw, unsigned long rate)
> +{
> + struct clk_hw *parent = clk_hw_get_parent(hw);
> + unsigned long parent_rate;
> +
> + if (IS_ERR(parent)) {
Will this ever happen? Collapse the WARN_ON into the if please:
if (WARN_ON(IS_ERR(parent)))
> + WARN_ON(1);
> + return;
> + }
> +
> + parent_rate = clk_hw_get_rate(parent);
> +
> + if (clk_frac_div_set_rate(hw, rate, parent_rate) < 0)
> + WARN_ON(1);
> +}
> +#endif
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index 09bccbb9640c..e4d124cc5657 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -841,6 +841,15 @@ int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
> int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
> u8 frac_width, u8 flags);
>
> +#ifdef CONFIG_PM_SLEEP
Can you remove this ifdef? It just complicates compilation testing.
> +void tegra_clk_pll_resume(struct clk *c, unsigned long rate);
> +void tegra_clk_divider_resume(struct clk_hw *hw, unsigned long rate);
> +void tegra_clk_pll_out_resume(struct clk *clk, unsigned long rate);
> +void tegra_clk_plle_tegra210_resume(struct clk *c);
> +void tegra_clk_sync_state_pll(struct clk *c);
> +void tegra_clk_sync_state_pll_out(struct clk *clk);
Do these APIs need to operate on struct clk? Why can't they operate on
clk_hw or why can't we drive the suspend/resume sequence from the clk
provider driver itself?
next prev parent reply other threads:[~2019-05-29 23:28 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-28 23:08 [PATCH V2 00/12] LP0 entry and exit support for Tegra210 Sowjanya Komatineni
2019-05-28 23:08 ` [PATCH V2 01/12] irqchip: tegra: do not disable COP IRQ during suspend Sowjanya Komatineni
2019-05-29 14:21 ` Thierry Reding
2019-05-28 23:08 ` [PATCH V2 02/12] pinctrl: tegra: add suspend and resume support Sowjanya Komatineni
2019-05-29 15:29 ` Dmitry Osipenko
2019-05-29 18:14 ` Sowjanya Komatineni
2019-05-29 19:32 ` Dmitry Osipenko
2019-05-29 20:11 ` Sowjanya Komatineni
2019-05-29 20:47 ` Dmitry Osipenko
2019-05-29 20:56 ` Sowjanya Komatineni
2019-05-29 21:07 ` Sowjanya Komatineni
2019-05-29 21:25 ` Dmitry Osipenko
2019-05-29 21:27 ` Sowjanya Komatineni
2019-05-29 21:33 ` Dmitry Osipenko
2019-05-28 23:08 ` [PATCH V2 03/12] clk: tegra: save and restore PLLs state for system Sowjanya Komatineni
2019-05-29 23:28 ` Stephen Boyd [this message]
2019-05-31 19:52 ` Sowjanya Komatineni
2019-06-05 23:31 ` Stephen Boyd
2019-05-28 23:08 ` [PATCH V2 04/12] clk: tegra: add support for peripheral clock suspend and resume Sowjanya Komatineni
2019-05-29 23:30 ` Stephen Boyd
2019-05-31 19:55 ` Sowjanya Komatineni
2019-05-28 23:08 ` [PATCH V2 05/12] clk: tegra: add support for OSC clock resume Sowjanya Komatineni
2019-05-28 23:08 ` [PATCH V2 06/12] clk: tegra: add suspend resume support for DFLL clock Sowjanya Komatineni
2019-06-04 12:41 ` Peter De Schrijver
2019-05-28 23:08 ` [PATCH V2 07/12] clk: tegra: support for Tegra210 clocks suspend-resume Sowjanya Komatineni
2019-06-06 18:17 ` Stephen Boyd
2019-06-06 19:13 ` Sowjanya Komatineni
2019-05-28 23:08 ` [PATCH V2 08/12] soc/tegra: pmc: allow support for more tegra wake models Sowjanya Komatineni
2019-05-29 14:30 ` Thierry Reding
2019-05-28 23:08 ` [PATCH V2 09/12] soc/tegra: pmc: add pmc wake support for tegra210 Sowjanya Komatineni
2019-05-29 5:42 ` JC Kuo
2019-05-29 13:52 ` Thierry Reding
2019-05-28 23:08 ` [PATCH V2 10/12] gpio: tegra: implement wake event support for Tegra210 and prior GPIO Sowjanya Komatineni
2019-05-29 14:03 ` Thierry Reding
2019-06-01 8:28 ` Sowjanya Komatineni
2019-05-28 23:08 ` [PATCH V2 11/12] arm64: tegra: enable wake from deep sleep on RTC alarm Sowjanya Komatineni
2019-05-28 23:08 ` [PATCH V2 12/12] soc/tegra: pmc: configure tegra deep sleep control settings Sowjanya Komatineni
2019-05-29 14:05 ` Thierry Reding
2019-05-29 14:12 ` [PATCH V2 00/12] LP0 entry and exit support for Tegra210 Thierry Reding
2019-06-04 13:47 ` Peter De Schrijver
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