Re: Re: [PATCH v2 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs

["jay.xu@rock-chips.com" <jay.xu@rock-chips.com>]

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Hi, Heiko

From: HeikoStübner
Date: 2019-05-29 16:06
To: Jianqun Xu
CC: mark.rutland; robh+dt; zhangzj; manivannan.sadhasivam; linux-rockchip; linux-arm-kernel; linux-kernel; devicetree
Subject: Re: [PATCH v2 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
Hi Jay,
 
Am Mittwoch, 29. Mai 2019, 09:47:52 CEST schrieb Jianqun Xu:
> This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
> include rk3399.dtsi. Also enable these nodes:
> - pcie/pcie_phy
> - sdhci/sdio/emmc/sdmmc
> 
> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
> ---
> changes since v1:
> - remove dfi and dmc
> 
>  arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 74 +++++++++++++++++++++
>  1 file changed, 74 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> new file mode 100644
> index 000000000000..b6d433ffa67d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> @@ -0,0 +1,74 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
> +
> +#include "rk3399.dtsi"
> +
> +/ {
> + compatible = "rockchip,rk3399pro";
> +
> + xin32k: xin32k {
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + clock-output-names = "xin32k";
> + #clock-cells = <0>;
> + };
 
Just to clarify, is the x32k clock really part of the soc itself?
Like on older SoCs it was always supplied from the pmic
or a separate rtc chip.
 
The 32K is not part of rk3399pro, it's from pmic.
 
> +};
> +
> +&emmc_phy {
> + status = "okay";
> +};
 
Is the emmc used inside the soc? As otherwise emmc / mmc controller
settings would be more a part of the actual board using the soc.
 
okay, it should be a part of the actual board using the soc, thank you
 
> +&pcie_phy {
> + status = "okay";
> +};
> +
> +&pcie0 {
> + ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
> + num-lanes = <4>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie_clkreqn_cpm>;
> + status = "okay";
> +};
 
This is probably needed as it needs to talk the rk1808
part over pcie, so it's really internal to the soc.
 
Yes, you are right
 
> +
> +&sdhci {
> + bus-width = <8>;
> + mmc-hs400-1_8v;
> + supports-emmc;
> + non-removable;
> + keep-power-in-suspend;
> + mmc-hs400-enhanced-strobe;
> + status = "okay";
> +};
 
Same comment as for emmc_phy above

okay, I will add comment here in next version
 
> +&sdio0 {
> + clock-frequency = <150000000>;
> + clock-freq-min-max = <200000 150000000>;
> + supports-sdio;
> + bus-width = <4>;
> + disable-wp;
> + cap-sd-highspeed;
> + cap-sdio-irq;
> + keep-power-in-suspend;
> + mmc-pwrseq = <&sdio_pwrseq>;
> + non-removable;
> + num-slots = <1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
> + sd-uhs-sdr104;
> + status = "okay";
> +};
 
Same comment as for emmc_phy above
okay
 
> +&sdmmc {
> + clock-frequency = <150000000>;
> + clock-freq-min-max = <400000 150000000>;
> + supports-sd;
> + bus-width = <4>;
> + cap-mmc-highspeed;
> + cap-sd-highspeed;
> + disable-wp;
> + num-slots = <1>;
> + vqmmc-supply = <&vccio_sd>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
> + status = "okay";
> +};
 
Same comment as for emmc_phy above
okay
 
 
 
 

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