From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Thu, 30 May 2019 07:55:50 +0800 From: "jay.xu@rock-chips.com" Subject: Re: Re: [PATCH v2 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs References: <20190528044850.23703-1-jay.xu@rock-chips.com>, <20190529074752.19388-1-jay.xu@rock-chips.com>, <5655934.Q7EnKghNLn@diego> Mime-Version: 1.0 Message-ID: <2019053007555014785438@rock-chips.com> Content-Type: multipart/alternative; boundary="----=_001_NextPart827721063133_=----" To: =?utf-8?B?SGVpa29TdMO8Ym5lcg==?= Cc: "mark.rutland" , robh+dt , zhangzj , "manivannan.sadhasivam" , linux-rockchip , linux-arm-kernel , linux-kernel , devicetree List-ID: This is a multi-part message in MIME format. ------=_001_NextPart827721063133_=---- Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 SGksIEhlaWtvDQoNCkZyb206IEhlaWtvU3TDvGJuZXINCkRhdGU6IDIwMTktMDUtMjkgMTY6MDYN ClRvOiBKaWFucXVuIFh1DQpDQzogbWFyay5ydXRsYW5kOyByb2JoK2R0OyB6aGFuZ3pqOyBtYW5p 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Hi, Heiko

<= div style=3D"border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0cm = 0cm 0cm">
Date: 2019-05-29 = 16:06
Subject:&nb= sp;Re: [PATCH v2 1/1] arm64: dts: rockchip: add core dtsi file for RK3399P= ro SoCs
Hi Jay,
=0A
 
=0AAm Mittwoch, 29. Mai 2019, 09:47:52 CEST schrieb Jianqun Xu:
=0A> This patch adds core dtsi file for Rockchip RK3399Pro SoCs,= =0A
> include rk3399.dtsi. Also enable these nodes:
=0A
&g= t; - pcie/pcie_phy
=0A
> - sdhci/sdio/emmc/sdmmc
=0A
= >
=0A
> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.co= m>
=0A
> ---
=0A
> changes since v1:
=0A> - remove dfi and dmc=0A
>
=0A
>  ar= ch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 74 +++++++++++++++++++++
= =0A
>  1 file changed, 74 insertions(+)
=0A
> = ; create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
=0A<= div>> =0A
> diff --git a/arch/arm64/boot/dts/rockchip/rk33= 99pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
=0A
>= new file mode 100644
=0A
> index 000000000000..b6d433ffa67d=0A
> --- /dev/null
=0A
> +++ b/arch/arm64/boot/dts= /rockchip/rk3399pro.dtsi
=0A
> @@ -0,0 +1,74 @@
=0A
&= gt; +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
=0A
> +// C= opyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
=0A
> = +
=0A
> +#include "rk3399.dtsi"
=0A
> +
=0A> +/ {
=0A
> + compatible =3D "rockchip,rk3399pro";=0A
> +
=0A
> + xin32k: xin32k {
=0A
> + = compatible =3D "fixed-clock";
=0A
> + clock-frequency =3D <= ;32768>;
=0A
> + clock-output-names =3D "xin32k";
=0A=
> + #clock-cells =3D <0>;
=0A
> + };
=0A 
=0A
Just to clarify, is the x32k clock really part of t= he soc itself?
=0A
Like on older SoCs it was always supplied from= the pmic
=0A
or a separate rtc chip.
=0A
 
The 32K is not part of rk3399pro, it's from pmic.=0A
 =0A
> +};
=0A
> +
=0A
> +&emmc_phy = {
=0A
> + status =3D "okay";
=0A
> +};
=0A 
=0A
Is the emmc used inside the soc? As otherwise emmc /= mmc controller
=0A
settings would be more a part of the actual b= oard using the soc.
=0A
 
okay, it should be = a part of the actual board using the soc, thank you
= =0A
 
=0A
> +&pcie_phy {
=0A
> + stat= us =3D "okay";
=0A
> +};
=0A
> +
=0A
>= +&pcie0 {
=0A
> + ep-gpios =3D <&gpio0 RK_PB4 GPIO= _ACTIVE_HIGH>;
=0A
> + num-lanes =3D <4>;
=0A> + pinctrl-names =3D "default";=0A
> + pinctrl-0 =3D &l= t;&pcie_clkreqn_cpm>;
=0A
> + status =3D "okay";
= =0A
> +};
=0A
 
=0A
This is probably needed = as it needs to talk the rk1808
=0A
part over pcie, so it's really= internal to the soc.
=0A
 
Yes, you are right=0A
 
=0A
> +
=0A
> +&sdhci {
= =0A
> + bus-width =3D <8>;
=0A
> + mmc-hs400-1_8v= ;
=0A
> + supports-emmc;
=0A
> + non-removable;=0A
> + keep-power-in-suspend;
=0A
> + mmc-hs400-enh= anced-strobe;
=0A
> + status =3D "okay";
=0A
> +};=
=0A
 
=0A
Same comment as for emmc_phy above
=

okay, I will add comment here in next version
=0A=
 
=0A
> +&sdio0 {
=0A
> + clock-freq= uency =3D <150000000>;
=0A
> + clock-freq-min-max =3D &l= t;200000 150000000>;
=0A
> + supports-sdio;
=0A
&g= t; + bus-width =3D <4>;
=0A
> + disable-wp;
=0A> + cap-sd-highspeed;
=0A
> + cap-sdio-irq;
=0A
&= gt; + keep-power-in-suspend;
=0A
> + mmc-pwrseq =3D <&s= dio_pwrseq>;
=0A
> + non-removable;
=0A
> + num= -slots =3D <1>;
=0A
> + pinctrl-names =3D "default";=0A
> + pinctrl-0 =3D <&sdio0_bus4 &sdio0_cmd &sdi= o0_clk>;
=0A
> + sd-uhs-sdr104;
=0A
> + status = =3D "okay";
=0A
> +};
=0A
 
=0A
Same co= mment as for emmc_phy above
okay
=0A
 
=0A> +&sdmmc {
=0A
> + clock-frequency =3D <150000000= >;
=0A
> + clock-freq-min-max =3D <400000 150000000>;=
=0A
> + supports-sd;
=0A
> + bus-width =3D <4&= gt;;
=0A
> + cap-mmc-highspeed;
=0A
> + cap-sd-hig= hspeed;
=0A
> + disable-wp;
=0A
> + num-slots =3D = <1>;
=0A
> + vqmmc-supply =3D <&vccio_sd>;=0A
> + pinctrl-names =3D "default";
=0A
> + pinctrl-= 0 =3D <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;=
=0A
> + status =3D "okay";
=0A
> +};
=0A 
=0A
Same comment as for emmc_phy above
okay=0A
 
=0A
 
=0A
 
=0A
&nbs= p;
=0A
=0A ------=_001_NextPart827721063133_=------